1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
2 # Copyright (c) 2009 Advanced Micro Devices, Inc.
5 # Redistribution and use in source and binary forms, with or without
6 # modification, are permitted provided that the following conditions are
7 # met: redistributions of source code must retain the above copyright
8 # notice, this list of conditions and the following disclaimer;
9 # redistributions in binary form must reproduce the above copyright
10 # notice, this list of conditions and the following disclaimer in the
11 # documentation and/or other materials provided with the distribution;
12 # neither the name of the copyright holders nor the names of its
13 # contributors may be used to endorse or promote products derived from
14 # this software without specific prior written permission.
16 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 # Authors: Brad Beckmann
32 from m5
.objects
import *
33 from m5
.defines
import buildEnv
34 from Ruby
import create_topology
37 # Note: the L1 Cache latency is only used by the sequencer on fast path hits
39 class L1Cache(RubyCache
):
43 # Note: the L2 Cache latency is not currently used
45 class L2Cache(RubyCache
):
48 def define_options(parser
):
51 def create_system(options
, full_system
, system
, dma_ports
, ruby_system
):
53 if buildEnv
['PROTOCOL'] != 'MESI_Two_Level':
54 fatal("This script requires the MESI_Two_Level protocol to be built.")
59 # The ruby network creation expects the list of nodes in the system to be
60 # consistent with the NetDest list. Therefore the l1 controller nodes must be
61 # listed before the directory nodes and directory nodes before dma nodes, etc.
69 # Must create the individual controllers before the network to ensure the
70 # controller constructors are called before the network constructor
72 l2_bits
= int(math
.log(options
.num_l2caches
, 2))
73 block_size_bits
= int(math
.log(options
.cacheline_size
, 2))
75 for i
in xrange(options
.num_cpus
):
77 # First create the Ruby objects associated with this cpu
79 l1i_cache
= L1Cache(size
= options
.l1i_size
,
80 assoc
= options
.l1i_assoc
,
81 start_index_bit
= block_size_bits
,
83 l1d_cache
= L1Cache(size
= options
.l1d_size
,
84 assoc
= options
.l1d_assoc
,
85 start_index_bit
= block_size_bits
,
88 prefetcher
= RubyPrefetcher
.Prefetcher()
90 l1_cntrl
= L1Cache_Controller(version
= i
,
93 l2_select_num_bits
= l2_bits
,
95 options
.cpu_type
== "detailed"),
96 prefetcher
= prefetcher
,
97 ruby_system
= ruby_system
,
98 clk_domain
=system
.cpu
[i
].clk_domain
,
99 transitions_per_cycle
=options
.ports
,
100 enable_prefetch
= False)
102 cpu_seq
= RubySequencer(version
= i
,
105 clk_domain
=system
.cpu
[i
].clk_domain
,
106 ruby_system
= ruby_system
)
108 l1_cntrl
.sequencer
= cpu_seq
109 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i
)
111 # Add controllers and sequencers to the appropriate lists
112 cpu_sequencers
.append(cpu_seq
)
113 l1_cntrl_nodes
.append(l1_cntrl
)
115 # Connect the L1 controllers and the network
116 l1_cntrl
.requestFromL1Cache
= ruby_system
.network
.slave
117 l1_cntrl
.responseFromL1Cache
= ruby_system
.network
.slave
118 l1_cntrl
.unblockFromL1Cache
= ruby_system
.network
.slave
120 l1_cntrl
.requestToL1Cache
= ruby_system
.network
.master
121 l1_cntrl
.responseToL1Cache
= ruby_system
.network
.master
124 l2_index_start
= block_size_bits
+ l2_bits
126 for i
in xrange(options
.num_l2caches
):
128 # First create the Ruby objects associated with this cpu
130 l2_cache
= L2Cache(size
= options
.l2_size
,
131 assoc
= options
.l2_assoc
,
132 start_index_bit
= l2_index_start
)
134 l2_cntrl
= L2Cache_Controller(version
= i
,
136 transitions_per_cycle
=options
.ports
,
137 ruby_system
= ruby_system
)
139 exec("ruby_system.l2_cntrl%d = l2_cntrl" % i
)
140 l2_cntrl_nodes
.append(l2_cntrl
)
142 # Connect the L2 controllers and the network
143 l2_cntrl
.DirRequestFromL2Cache
= ruby_system
.network
.slave
144 l2_cntrl
.L1RequestFromL2Cache
= ruby_system
.network
.slave
145 l2_cntrl
.responseFromL2Cache
= ruby_system
.network
.slave
147 l2_cntrl
.unblockToL2Cache
= ruby_system
.network
.master
148 l2_cntrl
.L1RequestToL2Cache
= ruby_system
.network
.master
149 l2_cntrl
.responseToL2Cache
= ruby_system
.network
.master
152 phys_mem_size
= sum(map(lambda r
: r
.size(), system
.mem_ranges
))
153 assert(phys_mem_size
% options
.num_dirs
== 0)
154 mem_module_size
= phys_mem_size
/ options
.num_dirs
157 # Run each of the ruby memory controllers at a ratio of the frequency of
159 # clk_divider value is a fix to pass regression.
160 ruby_system
.memctrl_clk_domain
= DerivedClockDomain(
161 clk_domain
=ruby_system
.clk_domain
,
164 for i
in xrange(options
.num_dirs
):
165 dir_size
= MemorySize('0B')
166 dir_size
.value
= mem_module_size
168 dir_cntrl
= Directory_Controller(version
= i
,
169 directory
= RubyDirectoryMemory(
170 version
= i
, size
= dir_size
),
171 transitions_per_cycle
= options
.ports
,
172 ruby_system
= ruby_system
)
174 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i
)
175 dir_cntrl_nodes
.append(dir_cntrl
)
177 # Connect the directory controllers and the network
178 dir_cntrl
.requestToDir
= ruby_system
.network
.master
179 dir_cntrl
.responseToDir
= ruby_system
.network
.master
180 dir_cntrl
.responseFromDir
= ruby_system
.network
.slave
183 for i
, dma_port
in enumerate(dma_ports
):
184 # Create the Ruby objects associated with the dma controller
185 dma_seq
= DMASequencer(version
= i
,
186 ruby_system
= ruby_system
,
189 dma_cntrl
= DMA_Controller(version
= i
,
190 dma_sequencer
= dma_seq
,
191 transitions_per_cycle
= options
.ports
,
192 ruby_system
= ruby_system
)
194 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i
)
195 dma_cntrl_nodes
.append(dma_cntrl
)
197 # Connect the dma controller to the network
198 dma_cntrl
.responseFromDir
= ruby_system
.network
.master
199 dma_cntrl
.requestToDir
= ruby_system
.network
.slave
201 all_cntrls
= l1_cntrl_nodes
+ \
206 # Create the io controller and the sequencer
208 io_seq
= DMASequencer(version
=len(dma_ports
), ruby_system
=ruby_system
)
209 ruby_system
._io
_port
= io_seq
210 io_controller
= DMA_Controller(version
= len(dma_ports
),
211 dma_sequencer
= io_seq
,
212 ruby_system
= ruby_system
)
213 ruby_system
.io_controller
= io_controller
215 # Connect the dma controller to the network
216 io_controller
.responseFromDir
= ruby_system
.network
.master
217 io_controller
.requestToDir
= ruby_system
.network
.slave
219 all_cntrls
= all_cntrls
+ [io_controller
]
221 topology
= create_topology(all_cntrls
, options
)
222 return (cpu_sequencers
, dir_cntrl_nodes
, topology
)