configs/ruby/MI_example.py

   1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
   2 # Copyright (c) 2009 Advanced Micro Devices, Inc.
   3 # All rights reserved.
   4 #
   5 # Redistribution and use in source and binary forms, with or without
   6 # modification, are permitted provided that the following conditions are
   7 # met: redistributions of source code must retain the above copyright
   8 # notice, this list of conditions and the following disclaimer;
   9 # redistributions in binary form must reproduce the above copyright
  10 # notice, this list of conditions and the following disclaimer in the
  11 # documentation and/or other materials provided with the distribution;
  12 # neither the name of the copyright holders nor the names of its
  13 # contributors may be used to endorse or promote products derived from
  14 # this software without specific prior written permission.
  15 #
  16 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27
  28 import math
  29 import m5
  30 from m5.objects import *
  31 from m5.defines import buildEnv
  32 from .Ruby import create_topology, create_directories
  33 from .Ruby import send_evicts
  34
  35 #
  36 # Declare caches used by the protocol
  37 #
  38 class L1Cache(RubyCache): pass
  39
  40 def define_options(parser):
  41     return
  42
  43 def create_system(options, full_system, system, dma_ports, bootmem,
  44                   ruby_system):
  45
  46     if buildEnv['PROTOCOL'] != 'MI_example':
  47         panic("This script requires the MI_example protocol to be built.")
  48
  49     cpu_sequencers = []
  50
  51     #
  52     # The ruby network creation expects the list of nodes in the system to be
  53     # consistent with the NetDest list.  Therefore the l1 controller nodes must be
  54     # listed before the directory nodes and directory nodes before dma nodes, etc.
  55     #
  56     l1_cntrl_nodes = []
  57     dma_cntrl_nodes = []
  58
  59     #
  60     # Must create the individual controllers before the network to ensure the
  61     # controller constructors are called before the network constructor
  62     #
  63     block_size_bits = int(math.log(options.cacheline_size, 2))
  64
  65     for i in range(options.num_cpus):
  66         #
  67         # First create the Ruby objects associated with this cpu
  68         # Only one cache exists for this protocol, so by default use the L1D
  69         # config parameters.
  70         #
  71         cache = L1Cache(size = options.l1d_size,
  72                         assoc = options.l1d_assoc,
  73                         start_index_bit = block_size_bits)
  74
  75
  76         # the ruby random tester reuses num_cpus to specify the
  77         # number of cpu ports connected to the tester object, which
  78         # is stored in system.cpu. because there is only ever one
  79         # tester object, num_cpus is not necessarily equal to the
  80         # size of system.cpu; therefore if len(system.cpu) == 1
  81         # we use system.cpu[0] to set the clk_domain, thereby ensuring
  82         # we don't index off the end of the cpu list.
  83         if len(system.cpu) == 1:
  84             clk_domain = system.cpu[0].clk_domain
  85         else:
  86             clk_domain = system.cpu[i].clk_domain
  87
  88         # Only one unified L1 cache exists. Can cache instructions and data.
  89         l1_cntrl = L1Cache_Controller(version=i, cacheMemory=cache,
  90                                       send_evictions=send_evicts(options),
  91                                       transitions_per_cycle=options.ports,
  92                                       clk_domain=clk_domain,
  93                                       ruby_system=ruby_system)
  94
  95         cpu_seq = RubySequencer(version=i, dcache=cache,
  96                                 clk_domain=clk_domain, ruby_system=ruby_system)
  97
  98         l1_cntrl.sequencer = cpu_seq
  99         exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
 100
 101         # Add controllers and sequencers to the appropriate lists
 102         cpu_sequencers.append(cpu_seq)
 103         l1_cntrl_nodes.append(l1_cntrl)
 104
 105         # Connect the L1 controllers and the network
 106         l1_cntrl.mandatoryQueue = MessageBuffer()
 107         l1_cntrl.requestFromCache = MessageBuffer(ordered = True)
 108         l1_cntrl.requestFromCache.master = ruby_system.network.slave
 109         l1_cntrl.responseFromCache = MessageBuffer(ordered = True)
 110         l1_cntrl.responseFromCache.master = ruby_system.network.slave
 111         l1_cntrl.forwardToCache = MessageBuffer(ordered = True)
 112         l1_cntrl.forwardToCache.slave = ruby_system.network.master
 113         l1_cntrl.responseToCache = MessageBuffer(ordered = True)
 114         l1_cntrl.responseToCache.slave = ruby_system.network.master
 115
 116     phys_mem_size = sum([r.size() for r in system.mem_ranges])
 117     assert(phys_mem_size % options.num_dirs == 0)
 118     mem_module_size = phys_mem_size / options.num_dirs
 119
 120     # Run each of the ruby memory controllers at a ratio of the frequency of
 121     # the ruby system.
 122     # clk_divider value is a fix to pass regression.
 123     ruby_system.memctrl_clk_domain = DerivedClockDomain(
 124                                           clk_domain=ruby_system.clk_domain,
 125                                           clk_divider=3)
 126
 127     mem_dir_cntrl_nodes, rom_dir_cntrl_node = create_directories(
 128         options, bootmem, ruby_system, system)
 129     dir_cntrl_nodes = mem_dir_cntrl_nodes[:]
 130     if rom_dir_cntrl_node is not None:
 131         dir_cntrl_nodes.append(rom_dir_cntrl_node)
 132     for dir_cntrl in dir_cntrl_nodes:
 133         # Connect the directory controllers and the network
 134         dir_cntrl.requestToDir = MessageBuffer(ordered = True)
 135         dir_cntrl.requestToDir.slave = ruby_system.network.master
 136         dir_cntrl.dmaRequestToDir = MessageBuffer(ordered = True)
 137         dir_cntrl.dmaRequestToDir.slave = ruby_system.network.master
 138
 139         dir_cntrl.responseFromDir = MessageBuffer()
 140         dir_cntrl.responseFromDir.master = ruby_system.network.slave
 141         dir_cntrl.dmaResponseFromDir = MessageBuffer(ordered = True)
 142         dir_cntrl.dmaResponseFromDir.master = ruby_system.network.slave
 143         dir_cntrl.forwardFromDir = MessageBuffer()
 144         dir_cntrl.forwardFromDir.master = ruby_system.network.slave
 145         dir_cntrl.requestToMemory = MessageBuffer()
 146         dir_cntrl.responseFromMemory = MessageBuffer()
 147
 148
 149     for i, dma_port in enumerate(dma_ports):
 150         #
 151         # Create the Ruby objects associated with the dma controller
 152         #
 153         dma_seq = DMASequencer(version = i,
 154                                ruby_system = ruby_system)
 155
 156         dma_cntrl = DMA_Controller(version = i,
 157                                    dma_sequencer = dma_seq,
 158                                    transitions_per_cycle = options.ports,
 159                                    ruby_system = ruby_system)
 160
 161         exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
 162         exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
 163         dma_cntrl_nodes.append(dma_cntrl)
 164
 165         # Connect the directory controllers and the network
 166         dma_cntrl.mandatoryQueue = MessageBuffer()
 167         dma_cntrl.requestToDir = MessageBuffer()
 168         dma_cntrl.requestToDir.master = ruby_system.network.slave
 169         dma_cntrl.responseFromDir = MessageBuffer(ordered = True)
 170         dma_cntrl.responseFromDir.slave = ruby_system.network.master
 171
 172     all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
 173
 174     # Create the io controller and the sequencer
 175     if full_system:
 176         io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system)
 177         ruby_system._io_port = io_seq
 178         io_controller = DMA_Controller(version = len(dma_ports),
 179                                        dma_sequencer = io_seq,
 180                                        ruby_system = ruby_system)
 181         ruby_system.io_controller = io_controller
 182
 183         # Connect the dma controller to the network
 184         io_controller.mandatoryQueue = MessageBuffer()
 185         io_controller.requestToDir = MessageBuffer()
 186         io_controller.requestToDir.master = ruby_system.network.slave
 187         io_controller.responseFromDir = MessageBuffer(ordered = True)
 188         io_controller.responseFromDir.slave = ruby_system.network.master
 189
 190         all_cntrls = all_cntrls + [io_controller]
 191
 192     ruby_system.network.number_of_virtual_networks = 5
 193     topology = create_topology(all_cntrls, options)
 194     return (cpu_sequencers, mem_dir_cntrl_nodes, topology)