1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
2 # Copyright (c) 2009 Advanced Micro Devices, Inc.
5 # Redistribution and use in source and binary forms, with or without
6 # modification, are permitted provided that the following conditions are
7 # met: redistributions of source code must retain the above copyright
8 # notice, this list of conditions and the following disclaimer;
9 # redistributions in binary form must reproduce the above copyright
10 # notice, this list of conditions and the following disclaimer in the
11 # documentation and/or other materials provided with the distribution;
12 # neither the name of the copyright holders nor the names of its
13 # contributors may be used to endorse or promote products derived from
14 # this software without specific prior written permission.
16 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 # Authors: Brad Beckmann
32 from m5
.objects
import *
33 from m5
.defines
import buildEnv
36 # Note: the cache latency is only used by the sequencer on fast path hits
38 class Cache(RubyCache
):
41 def define_options(parser
):
44 def create_system(options
, system
, piobus
, dma_devices
, ruby_system
):
46 if buildEnv
['PROTOCOL'] != 'MI_example':
47 panic("This script requires the MI_example protocol to be built.")
52 # The ruby network creation expects the list of nodes in the system to be
53 # consistent with the NetDest list. Therefore the l1 controller nodes must be
54 # listed before the directory nodes and directory nodes before dma nodes, etc.
61 # Must create the individual controllers before the network to ensure the
62 # controller constructors are called before the network constructor
64 block_size_bits
= int(math
.log(options
.cacheline_size
, 2))
68 for i
in xrange(options
.num_cpus
):
70 # First create the Ruby objects associated with this cpu
71 # Only one cache exists for this protocol, so by default use the L1D
74 cache
= Cache(size
= options
.l1d_size
,
75 assoc
= options
.l1d_assoc
,
76 start_index_bit
= block_size_bits
)
79 # Only one unified L1 cache exists. Can cache instructions and data.
81 l1_cntrl
= L1Cache_Controller(version
= i
,
82 cntrl_id
= cntrl_count
,
85 options
.cpu_type
== "detailed"),
86 ruby_system
= ruby_system
)
88 cpu_seq
= RubySequencer(version
= i
,
91 physMemPort
= system
.physmem
.port
,
92 physmem
= system
.physmem
,
93 ruby_system
= ruby_system
)
95 l1_cntrl
.sequencer
= cpu_seq
98 cpu_seq
.pio_port
= piobus
.port
100 exec("system.l1_cntrl%d = l1_cntrl" % i
)
102 # Add controllers and sequencers to the appropriate lists
104 cpu_sequencers
.append(cpu_seq
)
105 l1_cntrl_nodes
.append(l1_cntrl
)
109 phys_mem_size
= long(system
.physmem
.range.second
) - \
110 long(system
.physmem
.range.first
) + 1
111 mem_module_size
= phys_mem_size
/ options
.num_dirs
113 for i
in xrange(options
.num_dirs
):
115 # Create the Ruby objects associated with the directory controller
118 mem_cntrl
= RubyMemoryControl(version
= i
)
120 dir_size
= MemorySize('0B')
121 dir_size
.value
= mem_module_size
123 dir_cntrl
= Directory_Controller(version
= i
,
124 cntrl_id
= cntrl_count
,
126 RubyDirectoryMemory( \
129 use_map
= options
.use_map
,
132 memBuffer
= mem_cntrl
,
133 ruby_system
= ruby_system
)
135 exec("system.dir_cntrl%d = dir_cntrl" % i
)
136 dir_cntrl_nodes
.append(dir_cntrl
)
140 for i
, dma_device
in enumerate(dma_devices
):
142 # Create the Ruby objects associated with the dma controller
144 dma_seq
= DMASequencer(version
= i
,
145 physMemPort
= system
.physmem
.port
,
146 physmem
= system
.physmem
,
147 ruby_system
= ruby_system
)
149 dma_cntrl
= DMA_Controller(version
= i
,
150 cntrl_id
= cntrl_count
,
151 dma_sequencer
= dma_seq
,
152 ruby_system
= ruby_system
)
154 exec("system.dma_cntrl%d = dma_cntrl" % i
)
155 if dma_device
.type == 'MemTest':
156 exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i
)
158 exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i
)
159 dma_cntrl
.dma_sequencer
.port
= dma_device
.dma
160 dma_cntrl_nodes
.append(dma_cntrl
)
164 all_cntrls
= l1_cntrl_nodes
+ dir_cntrl_nodes
+ dma_cntrl_nodes
166 return (cpu_sequencers
, dir_cntrl_nodes
, all_cntrls
)