configs/ruby/MI_example.py

   1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
   2 # Copyright (c) 2009 Advanced Micro Devices, Inc.
   3 # All rights reserved.
   4 #
   5 # Redistribution and use in source and binary forms, with or without
   6 # modification, are permitted provided that the following conditions are
   7 # met: redistributions of source code must retain the above copyright
   8 # notice, this list of conditions and the following disclaimer;
   9 # redistributions in binary form must reproduce the above copyright
  10 # notice, this list of conditions and the following disclaimer in the
  11 # documentation and/or other materials provided with the distribution;
  12 # neither the name of the copyright holders nor the names of its
  13 # contributors may be used to endorse or promote products derived from
  14 # this software without specific prior written permission.
  15 #
  16 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27 #
  28 # Authors: Brad Beckmann
  29
  30 import math
  31 import m5
  32 from m5.objects import *
  33 from m5.defines import buildEnv
  34
  35 #
  36 # Note: the cache latency is only used by the sequencer on fast path hits
  37 #
  38 class Cache(RubyCache):
  39     latency = 3
  40
  41 def define_options(parser):
  42     return
  43
  44 def create_system(options, system, piobus, dma_devices, ruby_system):
  45
  46     if buildEnv['PROTOCOL'] != 'MI_example':
  47         panic("This script requires the MI_example protocol to be built.")
  48
  49     cpu_sequencers = []
  50
  51     #
  52     # The ruby network creation expects the list of nodes in the system to be
  53     # consistent with the NetDest list.  Therefore the l1 controller nodes must be
  54     # listed before the directory nodes and directory nodes before dma nodes, etc.
  55     #
  56     l1_cntrl_nodes = []
  57     dir_cntrl_nodes = []
  58     dma_cntrl_nodes = []
  59
  60     #
  61     # Must create the individual controllers before the network to ensure the
  62     # controller constructors are called before the network constructor
  63     #
  64     block_size_bits = int(math.log(options.cacheline_size, 2))
  65
  66     cntrl_count = 0
  67
  68     for i in xrange(options.num_cpus):
  69         #
  70         # First create the Ruby objects associated with this cpu
  71         # Only one cache exists for this protocol, so by default use the L1D
  72         # config parameters.
  73         #
  74         cache = Cache(size = options.l1d_size,
  75                       assoc = options.l1d_assoc,
  76                       start_index_bit = block_size_bits)
  77
  78         #
  79         # Only one unified L1 cache exists.  Can cache instructions and data.
  80         #
  81         l1_cntrl = L1Cache_Controller(version = i,
  82                                       cntrl_id = cntrl_count,
  83                                       cacheMemory = cache,
  84                                       send_evictions = (
  85                                           options.cpu_type == "detailed"),
  86                                       ruby_system = ruby_system)
  87
  88         cpu_seq = RubySequencer(version = i,
  89                                 icache = cache,
  90                                 dcache = cache,
  91                                 physMemPort = system.physmem.port,
  92                                 physmem = system.physmem,
  93                                 ruby_system = ruby_system)
  94
  95         l1_cntrl.sequencer = cpu_seq
  96
  97         if piobus != None:
  98             cpu_seq.pio_port = piobus.port
  99
 100         exec("system.l1_cntrl%d = l1_cntrl" % i)
 101         #
 102         # Add controllers and sequencers to the appropriate lists
 103         #
 104         cpu_sequencers.append(cpu_seq)
 105         l1_cntrl_nodes.append(l1_cntrl)
 106
 107         cntrl_count += 1
 108
 109     phys_mem_size = long(system.physmem.range.second) - \
 110                       long(system.physmem.range.first) + 1
 111     mem_module_size = phys_mem_size / options.num_dirs
 112
 113     for i in xrange(options.num_dirs):
 114         #
 115         # Create the Ruby objects associated with the directory controller
 116         #
 117
 118         mem_cntrl = RubyMemoryControl(version = i)
 119
 120         dir_size = MemorySize('0B')
 121         dir_size.value = mem_module_size
 122
 123         dir_cntrl = Directory_Controller(version = i,
 124                                          cntrl_id = cntrl_count,
 125                                          directory = \
 126                                          RubyDirectoryMemory( \
 127                                                     version = i,
 128                                                     size = dir_size,
 129                                                     use_map = options.use_map,
 130                                                     map_levels = \
 131                                                       options.map_levels),
 132                                          memBuffer = mem_cntrl,
 133                                          ruby_system = ruby_system)
 134
 135         exec("system.dir_cntrl%d = dir_cntrl" % i)
 136         dir_cntrl_nodes.append(dir_cntrl)
 137
 138         cntrl_count += 1
 139
 140     for i, dma_device in enumerate(dma_devices):
 141         #
 142         # Create the Ruby objects associated with the dma controller
 143         #
 144         dma_seq = DMASequencer(version = i,
 145                                physMemPort = system.physmem.port,
 146                                physmem = system.physmem,
 147                                ruby_system = ruby_system)
 148
 149         dma_cntrl = DMA_Controller(version = i,
 150                                    cntrl_id = cntrl_count,
 151                                    dma_sequencer = dma_seq,
 152                                    ruby_system = ruby_system)
 153
 154         exec("system.dma_cntrl%d = dma_cntrl" % i)
 155         if dma_device.type == 'MemTest':
 156             exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i)
 157         else:
 158             exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i)
 159         dma_cntrl.dma_sequencer.port = dma_device.dma
 160         dma_cntrl_nodes.append(dma_cntrl)
 161
 162         cntrl_count += 1
 163
 164     all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
 165
 166     return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)