configs/ruby/MOESI_CMP_directory.py

   1 # Copyright (c) 2019 ARM Limited
   2 # All rights reserved.
   3 #
   4 # The license below extends only to copyright in the software and shall
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  11 # modified or unmodified, in source code or in binary form.
  12 #
  13 # Copyright (c) 2006-2007 The Regents of The University of Michigan
  14 # Copyright (c) 2009 Advanced Micro Devices, Inc.
  15 # All rights reserved.
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  39
  40 import math
  41 import m5
  42 from m5.objects import *
  43 from m5.defines import buildEnv
  44 from .Ruby import create_topology, create_directories
  45 from .Ruby import send_evicts
  46
  47 #
  48 # Declare caches used by the protocol
  49 #
  50 class L1Cache(RubyCache):
  51     dataAccessLatency = 1
  52     tagAccessLatency = 1
  53
  54 class L2Cache(RubyCache):
  55     dataAccessLatency = 20
  56     tagAccessLatency = 20
  57
  58 def define_options(parser):
  59     return
  60
  61 def create_system(options, full_system, system, dma_ports, bootmem,
  62                   ruby_system):
  63
  64     if buildEnv['PROTOCOL'] != 'MOESI_CMP_directory':
  65         panic("This script requires the MOESI_CMP_directory protocol to be built.")
  66
  67     cpu_sequencers = []
  68
  69     #
  70     # The ruby network creation expects the list of nodes in the system to be
  71     # consistent with the NetDest list.  Therefore the l1 controller nodes must be
  72     # listed before the directory nodes and directory nodes before dma nodes, etc.
  73     #
  74     l1_cntrl_nodes = []
  75     l2_cntrl_nodes = []
  76     dma_cntrl_nodes = []
  77
  78     #
  79     # Must create the individual controllers before the network to ensure the
  80     # controller constructors are called before the network constructor
  81     #
  82     block_size_bits = int(math.log(options.cacheline_size, 2))
  83
  84     for i in range(options.num_cpus):
  85         #
  86         # First create the Ruby objects associated with this cpu
  87         #
  88         l1i_cache = L1Cache(size = options.l1i_size,
  89                             assoc = options.l1i_assoc,
  90                             start_index_bit = block_size_bits,
  91                             is_icache = True)
  92         l1d_cache = L1Cache(size = options.l1d_size,
  93                             assoc = options.l1d_assoc,
  94                             start_index_bit = block_size_bits,
  95                             is_icache = False)
  96
  97         # the ruby random tester reuses num_cpus to specify the
  98         # number of cpu ports connected to the tester object, which
  99         # is stored in system.cpu. because there is only ever one
 100         # tester object, num_cpus is not necessarily equal to the
 101         # size of system.cpu; therefore if len(system.cpu) == 1
 102         # we use system.cpu[0] to set the clk_domain, thereby ensuring
 103         # we don't index off the end of the cpu list.
 104         if len(system.cpu) == 1:
 105             clk_domain = system.cpu[0].clk_domain
 106         else:
 107             clk_domain = system.cpu[i].clk_domain
 108
 109         l1_cntrl = L1Cache_Controller(version=i, L1Icache=l1i_cache,
 110                                       L1Dcache=l1d_cache,
 111                                       send_evictions=send_evicts(options),
 112                                       transitions_per_cycle=options.ports,
 113                                       clk_domain=clk_domain,
 114                                       ruby_system=ruby_system)
 115
 116         cpu_seq = RubySequencer(version=i,
 117                                 dcache=l1d_cache, clk_domain=clk_domain,
 118                                 ruby_system=ruby_system)
 119
 120         l1_cntrl.sequencer = cpu_seq
 121         exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
 122
 123         # Add controllers and sequencers to the appropriate lists
 124         cpu_sequencers.append(cpu_seq)
 125         l1_cntrl_nodes.append(l1_cntrl)
 126
 127         # Connect the L1 controllers and the network
 128         l1_cntrl.mandatoryQueue = MessageBuffer()
 129         l1_cntrl.requestFromL1Cache = MessageBuffer()
 130         l1_cntrl.requestFromL1Cache.master = ruby_system.network.slave
 131         l1_cntrl.responseFromL1Cache = MessageBuffer()
 132         l1_cntrl.responseFromL1Cache.master = ruby_system.network.slave
 133         l1_cntrl.requestToL1Cache = MessageBuffer()
 134         l1_cntrl.requestToL1Cache.slave = ruby_system.network.master
 135         l1_cntrl.responseToL1Cache = MessageBuffer()
 136         l1_cntrl.responseToL1Cache.slave = ruby_system.network.master
 137         l1_cntrl.triggerQueue = MessageBuffer(ordered = True)
 138
 139
 140     # Create the L2s interleaved addr ranges
 141     l2_addr_ranges = []
 142     l2_bits = int(math.log(options.num_l2caches, 2))
 143     numa_bit = block_size_bits + l2_bits - 1
 144     sysranges = [] + system.mem_ranges
 145     if bootmem: sysranges.append(bootmem.range)
 146     for i in range(options.num_l2caches):
 147         ranges = []
 148         for r in sysranges:
 149             addr_range = AddrRange(r.start, size = r.size(),
 150                                     intlvHighBit = numa_bit,
 151                                     intlvBits = l2_bits,
 152                                     intlvMatch = i)
 153             ranges.append(addr_range)
 154         l2_addr_ranges.append(ranges)
 155
 156     for i in range(options.num_l2caches):
 157         #
 158         # First create the Ruby objects associated with this cpu
 159         #
 160         l2_cache = L2Cache(size = options.l2_size,
 161                            assoc = options.l2_assoc,
 162                            start_index_bit = block_size_bits + l2_bits)
 163
 164         l2_cntrl = L2Cache_Controller(version = i,
 165                                       L2cache = l2_cache,
 166                                       transitions_per_cycle = options.ports,
 167                                       ruby_system = ruby_system,
 168                                       addr_ranges = l2_addr_ranges[i])
 169
 170         exec("ruby_system.l2_cntrl%d = l2_cntrl" % i)
 171         l2_cntrl_nodes.append(l2_cntrl)
 172
 173         # Connect the L2 controllers and the network
 174         l2_cntrl.GlobalRequestFromL2Cache = MessageBuffer()
 175         l2_cntrl.GlobalRequestFromL2Cache.master = ruby_system.network.slave
 176         l2_cntrl.L1RequestFromL2Cache = MessageBuffer()
 177         l2_cntrl.L1RequestFromL2Cache.master = ruby_system.network.slave
 178         l2_cntrl.responseFromL2Cache = MessageBuffer()
 179         l2_cntrl.responseFromL2Cache.master = ruby_system.network.slave
 180
 181         l2_cntrl.GlobalRequestToL2Cache = MessageBuffer()
 182         l2_cntrl.GlobalRequestToL2Cache.slave = ruby_system.network.master
 183         l2_cntrl.L1RequestToL2Cache = MessageBuffer()
 184         l2_cntrl.L1RequestToL2Cache.slave = ruby_system.network.master
 185         l2_cntrl.responseToL2Cache = MessageBuffer()
 186         l2_cntrl.responseToL2Cache.slave = ruby_system.network.master
 187         l2_cntrl.triggerQueue = MessageBuffer(ordered = True)
 188
 189     # Run each of the ruby memory controllers at a ratio of the frequency of
 190     # the ruby system.
 191     # clk_divider value is a fix to pass regression.
 192     ruby_system.memctrl_clk_domain = DerivedClockDomain(
 193                                           clk_domain=ruby_system.clk_domain,
 194                                           clk_divider=3)
 195
 196
 197     mem_dir_cntrl_nodes, rom_dir_cntrl_node = create_directories(
 198         options, bootmem, ruby_system, system)
 199     dir_cntrl_nodes = mem_dir_cntrl_nodes[:]
 200     if rom_dir_cntrl_node is not None:
 201         dir_cntrl_nodes.append(rom_dir_cntrl_node)
 202     for dir_cntrl in dir_cntrl_nodes:
 203         # Connect the directory controllers and the network
 204         dir_cntrl.requestToDir = MessageBuffer()
 205         dir_cntrl.requestToDir.slave = ruby_system.network.master
 206         dir_cntrl.responseToDir = MessageBuffer()
 207         dir_cntrl.responseToDir.slave = ruby_system.network.master
 208         dir_cntrl.responseFromDir = MessageBuffer()
 209         dir_cntrl.responseFromDir.master = ruby_system.network.slave
 210         dir_cntrl.forwardFromDir = MessageBuffer()
 211         dir_cntrl.forwardFromDir.master = ruby_system.network.slave
 212         dir_cntrl.requestToMemory = MessageBuffer()
 213         dir_cntrl.responseFromMemory = MessageBuffer()
 214         dir_cntrl.triggerQueue = MessageBuffer(ordered = True)
 215
 216
 217     for i, dma_port in enumerate(dma_ports):
 218         #
 219         # Create the Ruby objects associated with the dma controller
 220         #
 221         dma_seq = DMASequencer(version = i,
 222                                ruby_system = ruby_system,
 223                                slave = dma_port)
 224
 225         dma_cntrl = DMA_Controller(version = i,
 226                                    dma_sequencer = dma_seq,
 227                                    transitions_per_cycle = options.ports,
 228                                    ruby_system = ruby_system)
 229
 230         exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
 231         dma_cntrl_nodes.append(dma_cntrl)
 232
 233         # Connect the dma controller to the network
 234         dma_cntrl.mandatoryQueue = MessageBuffer()
 235         dma_cntrl.responseFromDir = MessageBuffer()
 236         dma_cntrl.responseFromDir.slave = ruby_system.network.master
 237         dma_cntrl.reqToDir = MessageBuffer()
 238         dma_cntrl.reqToDir.master = ruby_system.network.slave
 239         dma_cntrl.respToDir = MessageBuffer()
 240         dma_cntrl.respToDir.master = ruby_system.network.slave
 241         dma_cntrl.triggerQueue = MessageBuffer(ordered = True)
 242
 243
 244     all_cntrls = l1_cntrl_nodes + \
 245                  l2_cntrl_nodes + \
 246                  dir_cntrl_nodes + \
 247                  dma_cntrl_nodes
 248
 249     # Create the io controller and the sequencer
 250     if full_system:
 251         io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system)
 252         ruby_system._io_port = io_seq
 253         io_controller = DMA_Controller(version = len(dma_ports),
 254                                        dma_sequencer = io_seq,
 255                                        ruby_system = ruby_system)
 256         ruby_system.io_controller = io_controller
 257
 258         # Connect the dma controller to the network
 259         io_controller.mandatoryQueue = MessageBuffer()
 260         io_controller.responseFromDir = MessageBuffer()
 261         io_controller.responseFromDir.slave = ruby_system.network.master
 262         io_controller.reqToDir = MessageBuffer()
 263         io_controller.reqToDir.master = ruby_system.network.slave
 264         io_controller.respToDir = MessageBuffer()
 265         io_controller.respToDir.master = ruby_system.network.slave
 266         io_controller.triggerQueue = MessageBuffer(ordered = True)
 267
 268         all_cntrls = all_cntrls + [io_controller]
 269
 270     ruby_system.network.number_of_virtual_networks = 3
 271     topology = create_topology(all_cntrls, options)
 272     return (cpu_sequencers, mem_dir_cntrl_nodes, topology)