1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
2 # Copyright (c) 2009 Advanced Micro Devices, Inc.
5 # Redistribution and use in source and binary forms, with or without
6 # modification, are permitted provided that the following conditions are
7 # met: redistributions of source code must retain the above copyright
8 # notice, this list of conditions and the following disclaimer;
9 # redistributions in binary form must reproduce the above copyright
10 # notice, this list of conditions and the following disclaimer in the
11 # documentation and/or other materials provided with the distribution;
12 # neither the name of the copyright holders nor the names of its
13 # contributors may be used to endorse or promote products derived from
14 # this software without specific prior written permission.
16 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 # Authors: Brad Beckmann
32 from m5
.objects
import *
33 from m5
.defines
import buildEnv
34 from Ruby
import create_topology
37 # Note: the L1 Cache latency is only used by the sequencer on fast path hits
39 class L1Cache(RubyCache
):
43 # Note: the L2 Cache latency is not currently used
45 class L2Cache(RubyCache
):
48 def define_options(parser
):
51 def create_system(options
, system
, piobus
, dma_ports
, ruby_system
):
53 if buildEnv
['PROTOCOL'] != 'MOESI_CMP_directory':
54 panic("This script requires the MOESI_CMP_directory protocol to be built.")
59 # The ruby network creation expects the list of nodes in the system to be
60 # consistent with the NetDest list. Therefore the l1 controller nodes must be
61 # listed before the directory nodes and directory nodes before dma nodes, etc.
69 # Must create the individual controllers before the network to ensure the
70 # controller constructors are called before the network constructor
72 l2_bits
= int(math
.log(options
.num_l2caches
, 2))
73 block_size_bits
= int(math
.log(options
.cacheline_size
, 2))
77 for i
in xrange(options
.num_cpus
):
79 # First create the Ruby objects associated with this cpu
81 l1i_cache
= L1Cache(size
= options
.l1i_size
,
82 assoc
= options
.l1i_assoc
,
83 start_index_bit
= block_size_bits
,
85 l1d_cache
= L1Cache(size
= options
.l1d_size
,
86 assoc
= options
.l1d_assoc
,
87 start_index_bit
= block_size_bits
,
90 l1_cntrl
= L1Cache_Controller(version
= i
,
91 cntrl_id
= cntrl_count
,
94 l2_select_num_bits
= l2_bits
,
96 options
.cpu_type
== "detailed"),
97 ruby_system
= ruby_system
)
99 cpu_seq
= RubySequencer(version
= i
,
102 ruby_system
= ruby_system
)
104 l1_cntrl
.sequencer
= cpu_seq
107 cpu_seq
.pio_port
= piobus
.slave
109 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i
)
111 # Add controllers and sequencers to the appropriate lists
113 cpu_sequencers
.append(cpu_seq
)
114 l1_cntrl_nodes
.append(l1_cntrl
)
118 l2_index_start
= block_size_bits
+ l2_bits
120 for i
in xrange(options
.num_l2caches
):
122 # First create the Ruby objects associated with this cpu
124 l2_cache
= L2Cache(size
= options
.l2_size
,
125 assoc
= options
.l2_assoc
,
126 start_index_bit
= l2_index_start
)
128 l2_cntrl
= L2Cache_Controller(version
= i
,
129 cntrl_id
= cntrl_count
,
131 ruby_system
= ruby_system
)
133 exec("ruby_system.l2_cntrl%d = l2_cntrl" % i
)
134 l2_cntrl_nodes
.append(l2_cntrl
)
138 phys_mem_size
= sum(map(lambda mem
: mem
.range.size(),
139 system
.memories
.unproxy(system
)))
140 mem_module_size
= phys_mem_size
/ options
.num_dirs
142 # Run each of the ruby memory controllers at a ratio of the frequency of
144 # clk_divider value is a fix to pass regression.
145 ruby_system
.memctrl_clk_domain
= DerivedClockDomain(
146 clk_domain
=ruby_system
.clk_domain
,
149 for i
in xrange(options
.num_dirs
):
151 # Create the Ruby objects associated with the directory controller
154 mem_cntrl
= RubyMemoryControl(
155 clk_domain
= ruby_system
.memctrl_clk_domain
,
157 ruby_system
= ruby_system
)
159 dir_size
= MemorySize('0B')
160 dir_size
.value
= mem_module_size
162 dir_cntrl
= Directory_Controller(version
= i
,
163 cntrl_id
= cntrl_count
,
165 RubyDirectoryMemory(version
= i
,
167 use_map
= options
.use_map
),
168 memBuffer
= mem_cntrl
,
169 ruby_system
= ruby_system
)
171 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i
)
172 dir_cntrl_nodes
.append(dir_cntrl
)
176 for i
, dma_port
in enumerate(dma_ports
):
178 # Create the Ruby objects associated with the dma controller
180 dma_seq
= DMASequencer(version
= i
,
181 ruby_system
= ruby_system
)
183 dma_cntrl
= DMA_Controller(version
= i
,
184 cntrl_id
= cntrl_count
,
185 dma_sequencer
= dma_seq
,
186 ruby_system
= ruby_system
)
188 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i
)
189 exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i
)
190 dma_cntrl_nodes
.append(dma_cntrl
)
193 all_cntrls
= l1_cntrl_nodes
+ \
198 topology
= create_topology(all_cntrls
, options
)
200 return (cpu_sequencers
, dir_cntrl_nodes
, topology
)