1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
2 # Copyright (c) 2009 Advanced Micro Devices, Inc.
5 # Redistribution and use in source and binary forms, with or without
6 # modification, are permitted provided that the following conditions are
7 # met: redistributions of source code must retain the above copyright
8 # notice, this list of conditions and the following disclaimer;
9 # redistributions in binary form must reproduce the above copyright
10 # notice, this list of conditions and the following disclaimer in the
11 # documentation and/or other materials provided with the distribution;
12 # neither the name of the copyright holders nor the names of its
13 # contributors may be used to endorse or promote products derived from
14 # this software without specific prior written permission.
16 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 # Authors: Brad Beckmann
32 from m5
.objects
import *
33 from m5
.defines
import buildEnv
36 # Note: the L1 Cache latency is only used by the sequencer on fast path hits
38 class L1Cache(RubyCache
):
42 # Note: the L2 Cache latency is not currently used
44 class L2Cache(RubyCache
):
47 def define_options(parser
):
50 def create_system(options
, system
, piobus
, dma_devices
, ruby_system
):
52 if buildEnv
['PROTOCOL'] != 'MOESI_CMP_directory':
53 panic("This script requires the MOESI_CMP_directory protocol to be built.")
58 # The ruby network creation expects the list of nodes in the system to be
59 # consistent with the NetDest list. Therefore the l1 controller nodes must be
60 # listed before the directory nodes and directory nodes before dma nodes, etc.
68 # Must create the individual controllers before the network to ensure the
69 # controller constructors are called before the network constructor
71 l2_bits
= int(math
.log(options
.num_l2caches
, 2))
72 block_size_bits
= int(math
.log(options
.cacheline_size
, 2))
76 for i
in xrange(options
.num_cpus
):
78 # First create the Ruby objects associated with this cpu
80 l1i_cache
= L1Cache(size
= options
.l1i_size
,
81 assoc
= options
.l1i_assoc
,
82 start_index_bit
= block_size_bits
)
83 l1d_cache
= L1Cache(size
= options
.l1d_size
,
84 assoc
= options
.l1d_assoc
,
85 start_index_bit
= block_size_bits
)
87 l1_cntrl
= L1Cache_Controller(version
= i
,
88 cntrl_id
= cntrl_count
,
89 L1IcacheMemory
= l1i_cache
,
90 L1DcacheMemory
= l1d_cache
,
91 l2_select_num_bits
= l2_bits
,
93 options
.cpu_type
== "detailed"),
94 ruby_system
= ruby_system
)
96 cpu_seq
= RubySequencer(version
= i
,
99 physMemPort
= system
.physmem
.port
,
100 physmem
= system
.physmem
,
101 ruby_system
= ruby_system
)
103 l1_cntrl
.sequencer
= cpu_seq
106 cpu_seq
.pio_port
= piobus
.port
108 exec("system.l1_cntrl%d = l1_cntrl" % i
)
110 # Add controllers and sequencers to the appropriate lists
112 cpu_sequencers
.append(cpu_seq
)
113 l1_cntrl_nodes
.append(l1_cntrl
)
117 l2_index_start
= block_size_bits
+ l2_bits
119 for i
in xrange(options
.num_l2caches
):
121 # First create the Ruby objects associated with this cpu
123 l2_cache
= L2Cache(size
= options
.l2_size
,
124 assoc
= options
.l2_assoc
,
125 start_index_bit
= l2_index_start
)
127 l2_cntrl
= L2Cache_Controller(version
= i
,
128 cntrl_id
= cntrl_count
,
129 L2cacheMemory
= l2_cache
,
130 ruby_system
= ruby_system
)
132 exec("system.l2_cntrl%d = l2_cntrl" % i
)
133 l2_cntrl_nodes
.append(l2_cntrl
)
137 phys_mem_size
= long(system
.physmem
.range.second
) - \
138 long(system
.physmem
.range.first
) + 1
139 mem_module_size
= phys_mem_size
/ options
.num_dirs
141 for i
in xrange(options
.num_dirs
):
143 # Create the Ruby objects associated with the directory controller
146 mem_cntrl
= RubyMemoryControl(version
= i
)
148 dir_size
= MemorySize('0B')
149 dir_size
.value
= mem_module_size
151 dir_cntrl
= Directory_Controller(version
= i
,
152 cntrl_id
= cntrl_count
,
154 RubyDirectoryMemory(version
= i
,
156 memBuffer
= mem_cntrl
,
157 ruby_system
= ruby_system
)
159 exec("system.dir_cntrl%d = dir_cntrl" % i
)
160 dir_cntrl_nodes
.append(dir_cntrl
)
164 for i
, dma_device
in enumerate(dma_devices
):
166 # Create the Ruby objects associated with the dma controller
168 dma_seq
= DMASequencer(version
= i
,
169 physMemPort
= system
.physmem
.port
,
170 physmem
= system
.physmem
,
171 ruby_system
= ruby_system
)
173 dma_cntrl
= DMA_Controller(version
= i
,
174 cntrl_id
= cntrl_count
,
175 dma_sequencer
= dma_seq
,
176 ruby_system
= ruby_system
)
178 exec("system.dma_cntrl%d = dma_cntrl" % i
)
179 if dma_device
.type == 'MemTest':
180 exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i
)
182 exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i
)
183 dma_cntrl_nodes
.append(dma_cntrl
)
187 all_cntrls
= l1_cntrl_nodes
+ \
192 return (cpu_sequencers
, dir_cntrl_nodes
, all_cntrls
)