configs/ruby/MOESI_CMP_token.py

   1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
   2 # Copyright (c) 2009 Advanced Micro Devices, Inc.
   3 # All rights reserved.
   4 #
   5 # Redistribution and use in source and binary forms, with or without
   6 # modification, are permitted provided that the following conditions are
   7 # met: redistributions of source code must retain the above copyright
   8 # notice, this list of conditions and the following disclaimer;
   9 # redistributions in binary form must reproduce the above copyright
  10 # notice, this list of conditions and the following disclaimer in the
  11 # documentation and/or other materials provided with the distribution;
  12 # neither the name of the copyright holders nor the names of its
  13 # contributors may be used to endorse or promote products derived from
  14 # this software without specific prior written permission.
  15 #
  16 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27
  28 import math
  29 import m5
  30 from m5.objects import *
  31 from m5.defines import buildEnv
  32 from .Ruby import create_topology, create_directories
  33 from .Ruby import send_evicts
  34
  35 #
  36 # Declare caches used by the protocol
  37 #
  38 class L1Cache(RubyCache): pass
  39 class L2Cache(RubyCache): pass
  40
  41 def define_options(parser):
  42     parser.add_option("--l1-retries", type="int", default=1,
  43                       help="Token_CMP: # of l1 retries before going persistent")
  44     parser.add_option("--timeout-latency", type="int", default=300,
  45                       help="Token_CMP: cycles until issuing again");
  46     parser.add_option("--disable-dyn-timeouts", action="store_true",
  47           help="Token_CMP: disable dyanimc timeouts, use fixed latency instead")
  48     parser.add_option("--allow-atomic-migration", action="store_true",
  49           help="allow migratory sharing for atomic only accessed blocks")
  50
  51 def create_system(options, full_system, system, dma_ports, bootmem,
  52                   ruby_system):
  53
  54     if buildEnv['PROTOCOL'] != 'MOESI_CMP_token':
  55         panic("This script requires the MOESI_CMP_token protocol to be built.")
  56
  57     #
  58     # number of tokens that the owner passes to requests so that shared blocks can
  59     # respond to read requests
  60     #
  61     n_tokens = options.num_cpus + 1
  62
  63     cpu_sequencers = []
  64
  65     #
  66     # The ruby network creation expects the list of nodes in the system to be
  67     # consistent with the NetDest list.  Therefore the l1 controller nodes must be
  68     # listed before the directory nodes and directory nodes before dma nodes, etc.
  69     #
  70     l1_cntrl_nodes = []
  71     l2_cntrl_nodes = []
  72     dma_cntrl_nodes = []
  73
  74     #
  75     # Must create the individual controllers before the network to ensure the
  76     # controller constructors are called before the network constructor
  77     #
  78     l2_bits = int(math.log(options.num_l2caches, 2))
  79     block_size_bits = int(math.log(options.cacheline_size, 2))
  80
  81     for i in range(options.num_cpus):
  82         #
  83         # First create the Ruby objects associated with this cpu
  84         #
  85         l1i_cache = L1Cache(size = options.l1i_size,
  86                             assoc = options.l1i_assoc,
  87                             start_index_bit = block_size_bits)
  88         l1d_cache = L1Cache(size = options.l1d_size,
  89                             assoc = options.l1d_assoc,
  90                             start_index_bit = block_size_bits)
  91
  92         # the ruby random tester reuses num_cpus to specify the
  93         # number of cpu ports connected to the tester object, which
  94         # is stored in system.cpu. because there is only ever one
  95         # tester object, num_cpus is not necessarily equal to the
  96         # size of system.cpu; therefore if len(system.cpu) == 1
  97         # we use system.cpu[0] to set the clk_domain, thereby ensuring
  98         # we don't index off the end of the cpu list.
  99         if len(system.cpu) == 1:
 100             clk_domain = system.cpu[0].clk_domain
 101         else:
 102             clk_domain = system.cpu[i].clk_domain
 103
 104         l1_cntrl = L1Cache_Controller(version=i, L1Icache=l1i_cache,
 105                                       L1Dcache=l1d_cache,
 106                                       l2_select_num_bits=l2_bits,
 107                                       N_tokens=n_tokens,
 108                                       retry_threshold=options.l1_retries,
 109                                       fixed_timeout_latency=\
 110                                       options.timeout_latency,
 111                                       dynamic_timeout_enabled=\
 112                                       not options.disable_dyn_timeouts,
 113                                       no_mig_atomic=not \
 114                                       options.allow_atomic_migration,
 115                                       send_evictions=send_evicts(options),
 116                                       transitions_per_cycle=options.ports,
 117                                       clk_domain=clk_domain,
 118                                       ruby_system=ruby_system)
 119
 120         cpu_seq = RubySequencer(version=i,
 121                                 dcache=l1d_cache, clk_domain=clk_domain,
 122                                 ruby_system=ruby_system)
 123
 124         l1_cntrl.sequencer = cpu_seq
 125         exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
 126
 127         # Add controllers and sequencers to the appropriate lists
 128         cpu_sequencers.append(cpu_seq)
 129         l1_cntrl_nodes.append(l1_cntrl)
 130
 131         # Connect the L1 controllers and the network
 132         l1_cntrl.requestFromL1Cache = MessageBuffer()
 133         l1_cntrl.requestFromL1Cache.master = ruby_system.network.slave
 134         l1_cntrl.responseFromL1Cache = MessageBuffer()
 135         l1_cntrl.responseFromL1Cache.master = ruby_system.network.slave
 136         l1_cntrl.persistentFromL1Cache = MessageBuffer(ordered = True)
 137         l1_cntrl.persistentFromL1Cache.master = ruby_system.network.slave
 138
 139         l1_cntrl.mandatoryQueue = MessageBuffer()
 140         l1_cntrl.requestToL1Cache = MessageBuffer()
 141         l1_cntrl.requestToL1Cache.slave = ruby_system.network.master
 142         l1_cntrl.responseToL1Cache = MessageBuffer()
 143         l1_cntrl.responseToL1Cache.slave = ruby_system.network.master
 144         l1_cntrl.persistentToL1Cache = MessageBuffer(ordered = True)
 145         l1_cntrl.persistentToL1Cache.slave = ruby_system.network.master
 146
 147
 148     l2_index_start = block_size_bits + l2_bits
 149
 150     for i in range(options.num_l2caches):
 151         #
 152         # First create the Ruby objects associated with this cpu
 153         #
 154         l2_cache = L2Cache(size = options.l2_size,
 155                            assoc = options.l2_assoc,
 156                            start_index_bit = l2_index_start)
 157
 158         l2_cntrl = L2Cache_Controller(version = i,
 159                                       L2cache = l2_cache,
 160                                       N_tokens = n_tokens,
 161                                       transitions_per_cycle = options.ports,
 162                                       ruby_system = ruby_system)
 163
 164         exec("ruby_system.l2_cntrl%d = l2_cntrl" % i)
 165         l2_cntrl_nodes.append(l2_cntrl)
 166
 167         # Connect the L2 controllers and the network
 168         l2_cntrl.GlobalRequestFromL2Cache = MessageBuffer()
 169         l2_cntrl.GlobalRequestFromL2Cache.master = ruby_system.network.slave
 170         l2_cntrl.L1RequestFromL2Cache = MessageBuffer()
 171         l2_cntrl.L1RequestFromL2Cache.master = ruby_system.network.slave
 172         l2_cntrl.responseFromL2Cache = MessageBuffer()
 173         l2_cntrl.responseFromL2Cache.master = ruby_system.network.slave
 174
 175         l2_cntrl.GlobalRequestToL2Cache = MessageBuffer()
 176         l2_cntrl.GlobalRequestToL2Cache.slave = ruby_system.network.master
 177         l2_cntrl.L1RequestToL2Cache = MessageBuffer()
 178         l2_cntrl.L1RequestToL2Cache.slave = ruby_system.network.master
 179         l2_cntrl.responseToL2Cache = MessageBuffer()
 180         l2_cntrl.responseToL2Cache.slave = ruby_system.network.master
 181         l2_cntrl.persistentToL2Cache = MessageBuffer(ordered = True)
 182         l2_cntrl.persistentToL2Cache.slave = ruby_system.network.master
 183
 184
 185     # Run each of the ruby memory controllers at a ratio of the frequency of
 186     # the ruby system
 187     # clk_divider value is a fix to pass regression.
 188     ruby_system.memctrl_clk_domain = DerivedClockDomain(
 189                                           clk_domain=ruby_system.clk_domain,
 190                                           clk_divider=3)
 191
 192     mem_dir_cntrl_nodes, rom_dir_cntrl_node = create_directories(
 193         options, bootmem, ruby_system, system)
 194     dir_cntrl_nodes = mem_dir_cntrl_nodes[:]
 195     if rom_dir_cntrl_node is not None:
 196         dir_cntrl_nodes.append(rom_dir_cntrl_node)
 197     for dir_cntrl in dir_cntrl_nodes:
 198         dir_cntrl.l2_select_num_bits = l2_bits
 199         # Connect the directory controllers and the network
 200         dir_cntrl.requestToDir = MessageBuffer()
 201         dir_cntrl.requestToDir.slave = ruby_system.network.master
 202         dir_cntrl.responseToDir = MessageBuffer()
 203         dir_cntrl.responseToDir.slave = ruby_system.network.master
 204         dir_cntrl.persistentToDir = MessageBuffer(ordered = True)
 205         dir_cntrl.persistentToDir.slave = ruby_system.network.master
 206         dir_cntrl.dmaRequestToDir = MessageBuffer(ordered = True)
 207         dir_cntrl.dmaRequestToDir.slave = ruby_system.network.master
 208
 209         dir_cntrl.requestFromDir = MessageBuffer()
 210         dir_cntrl.requestFromDir.master = ruby_system.network.slave
 211         dir_cntrl.responseFromDir = MessageBuffer()
 212         dir_cntrl.responseFromDir.master = ruby_system.network.slave
 213         dir_cntrl.persistentFromDir = MessageBuffer(ordered = True)
 214         dir_cntrl.persistentFromDir.master = ruby_system.network.slave
 215         dir_cntrl.dmaResponseFromDir = MessageBuffer(ordered = True)
 216         dir_cntrl.dmaResponseFromDir.master = ruby_system.network.slave
 217         dir_cntrl.requestToMemory = MessageBuffer()
 218         dir_cntrl.responseFromMemory = MessageBuffer()
 219
 220
 221     for i, dma_port in enumerate(dma_ports):
 222         #
 223         # Create the Ruby objects associated with the dma controller
 224         #
 225         dma_seq = DMASequencer(version = i,
 226                                ruby_system = ruby_system,
 227                                slave = dma_port)
 228
 229         dma_cntrl = DMA_Controller(version = i,
 230                                    dma_sequencer = dma_seq,
 231                                    transitions_per_cycle = options.ports,
 232                                    ruby_system = ruby_system)
 233
 234         exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
 235         dma_cntrl_nodes.append(dma_cntrl)
 236
 237         # Connect the dma controller to the network
 238         dma_cntrl.mandatoryQueue = MessageBuffer()
 239         dma_cntrl.responseFromDir = MessageBuffer(ordered = True)
 240         dma_cntrl.responseFromDir.slave = ruby_system.network.master
 241         dma_cntrl.reqToDirectory = MessageBuffer()
 242         dma_cntrl.reqToDirectory.master = ruby_system.network.slave
 243
 244     all_cntrls = l1_cntrl_nodes + \
 245                  l2_cntrl_nodes + \
 246                  dir_cntrl_nodes + \
 247                  dma_cntrl_nodes
 248
 249     # Create the io controller and the sequencer
 250     if full_system:
 251         io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system)
 252         ruby_system._io_port = io_seq
 253         io_controller = DMA_Controller(version = len(dma_ports),
 254                                        dma_sequencer = io_seq,
 255                                        ruby_system = ruby_system)
 256         ruby_system.io_controller = io_controller
 257
 258         # Connect the dma controller to the network
 259         io_controller.mandatoryQueue = MessageBuffer()
 260         io_controller.responseFromDir = MessageBuffer(ordered = True)
 261         io_controller.responseFromDir.slave = ruby_system.network.master
 262         io_controller.reqToDirectory = MessageBuffer()
 263         io_controller.reqToDirectory.master = ruby_system.network.slave
 264
 265         all_cntrls = all_cntrls + [io_controller]
 266
 267     ruby_system.network.number_of_virtual_networks = 6
 268     topology = create_topology(all_cntrls, options)
 269     return (cpu_sequencers, mem_dir_cntrl_nodes, topology)