1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
2 # Copyright (c) 2009 Advanced Micro Devices, Inc.
5 # Redistribution and use in source and binary forms, with or without
6 # modification, are permitted provided that the following conditions are
7 # met: redistributions of source code must retain the above copyright
8 # notice, this list of conditions and the following disclaimer;
9 # redistributions in binary form must reproduce the above copyright
10 # notice, this list of conditions and the following disclaimer in the
11 # documentation and/or other materials provided with the distribution;
12 # neither the name of the copyright holders nor the names of its
13 # contributors may be used to endorse or promote products derived from
14 # this software without specific prior written permission.
16 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 # Authors: Brad Beckmann
32 from m5
.objects
import *
33 from m5
.defines
import buildEnv
34 from Ruby
import create_topology
37 # Note: the L1 Cache latency is only used by the sequencer on fast path hits
39 class L1Cache(RubyCache
):
43 # Note: the L2 Cache latency is not currently used
45 class L2Cache(RubyCache
):
48 def define_options(parser
):
49 parser
.add_option("--l1-retries", type="int", default
=1,
50 help="Token_CMP: # of l1 retries before going persistent")
51 parser
.add_option("--timeout-latency", type="int", default
=300,
52 help="Token_CMP: cycles until issuing again");
53 parser
.add_option("--disable-dyn-timeouts", action
="store_true",
54 help="Token_CMP: disable dyanimc timeouts, use fixed latency instead")
55 parser
.add_option("--allow-atomic-migration", action
="store_true",
56 help="allow migratory sharing for atomic only accessed blocks")
58 def create_system(options
, system
, piobus
, dma_ports
, ruby_system
):
60 if buildEnv
['PROTOCOL'] != 'MOESI_CMP_token':
61 panic("This script requires the MOESI_CMP_token protocol to be built.")
64 # number of tokens that the owner passes to requests so that shared blocks can
65 # respond to read requests
67 n_tokens
= options
.num_cpus
+ 1
72 # The ruby network creation expects the list of nodes in the system to be
73 # consistent with the NetDest list. Therefore the l1 controller nodes must be
74 # listed before the directory nodes and directory nodes before dma nodes, etc.
82 # Must create the individual controllers before the network to ensure the
83 # controller constructors are called before the network constructor
85 l2_bits
= int(math
.log(options
.num_l2caches
, 2))
86 block_size_bits
= int(math
.log(options
.cacheline_size
, 2))
88 for i
in xrange(options
.num_cpus
):
90 # First create the Ruby objects associated with this cpu
92 l1i_cache
= L1Cache(size
= options
.l1i_size
,
93 assoc
= options
.l1i_assoc
,
94 start_index_bit
= block_size_bits
)
95 l1d_cache
= L1Cache(size
= options
.l1d_size
,
96 assoc
= options
.l1d_assoc
,
97 start_index_bit
= block_size_bits
)
99 l1_cntrl
= L1Cache_Controller(version
= i
,
100 L1Icache
= l1i_cache
,
101 L1Dcache
= l1d_cache
,
102 l2_select_num_bits
= l2_bits
,
106 fixed_timeout_latency
= \
107 options
.timeout_latency
,
108 dynamic_timeout_enabled
= \
109 not options
.disable_dyn_timeouts
,
110 no_mig_atomic
= not \
111 options
.allow_atomic_migration
,
113 options
.cpu_type
== "detailed"),
114 transitions_per_cycle
= options
.ports
,
115 ruby_system
= ruby_system
)
117 cpu_seq
= RubySequencer(version
= i
,
120 ruby_system
= ruby_system
)
122 l1_cntrl
.sequencer
= cpu_seq
125 cpu_seq
.pio_master_port
= piobus
.slave
126 cpu_seq
.mem_master_port
= piobus
.slave
127 cpu_seq
.pio_slave_port
= piobus
.master
129 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i
)
131 # Add controllers and sequencers to the appropriate lists
133 cpu_sequencers
.append(cpu_seq
)
134 l1_cntrl_nodes
.append(l1_cntrl
)
136 l2_index_start
= block_size_bits
+ l2_bits
138 for i
in xrange(options
.num_l2caches
):
140 # First create the Ruby objects associated with this cpu
142 l2_cache
= L2Cache(size
= options
.l2_size
,
143 assoc
= options
.l2_assoc
,
144 start_index_bit
= l2_index_start
)
146 l2_cntrl
= L2Cache_Controller(version
= i
,
149 transitions_per_cycle
= options
.ports
,
150 ruby_system
= ruby_system
)
152 exec("ruby_system.l2_cntrl%d = l2_cntrl" % i
)
153 l2_cntrl_nodes
.append(l2_cntrl
)
155 phys_mem_size
= sum(map(lambda r
: r
.size(), system
.mem_ranges
))
156 assert(phys_mem_size
% options
.num_dirs
== 0)
157 mem_module_size
= phys_mem_size
/ options
.num_dirs
159 # Run each of the ruby memory controllers at a ratio of the frequency of
161 # clk_divider value is a fix to pass regression.
162 ruby_system
.memctrl_clk_domain
= DerivedClockDomain(
163 clk_domain
=ruby_system
.clk_domain
,
166 for i
in xrange(options
.num_dirs
):
168 # Create the Ruby objects associated with the directory controller
171 mem_cntrl
= RubyMemoryControl(
172 clk_domain
= ruby_system
.memctrl_clk_domain
,
174 ruby_system
= ruby_system
)
176 dir_size
= MemorySize('0B')
177 dir_size
.value
= mem_module_size
179 dir_cntrl
= Directory_Controller(version
= i
,
181 RubyDirectoryMemory(version
= i
,
182 use_map
= options
.use_map
,
184 memBuffer
= mem_cntrl
,
185 l2_select_num_bits
= l2_bits
,
186 transitions_per_cycle
= options
.ports
,
187 ruby_system
= ruby_system
)
189 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i
)
190 dir_cntrl_nodes
.append(dir_cntrl
)
192 for i
, dma_port
in enumerate(dma_ports
):
194 # Create the Ruby objects associated with the dma controller
196 dma_seq
= DMASequencer(version
= i
,
197 ruby_system
= ruby_system
)
199 dma_cntrl
= DMA_Controller(version
= i
,
200 dma_sequencer
= dma_seq
,
201 transitions_per_cycle
= options
.ports
,
202 ruby_system
= ruby_system
)
204 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i
)
205 exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i
)
206 dma_cntrl_nodes
.append(dma_cntrl
)
208 all_cntrls
= l1_cntrl_nodes
+ \
213 topology
= create_topology(all_cntrls
, options
)
215 return (cpu_sequencers
, dir_cntrl_nodes
, topology
)