configs/ruby/MOESI_CMP_token.py

   1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
   2 # Copyright (c) 2009 Advanced Micro Devices, Inc.
   3 # All rights reserved.
   4 #
   5 # Redistribution and use in source and binary forms, with or without
   6 # modification, are permitted provided that the following conditions are
   7 # met: redistributions of source code must retain the above copyright
   8 # notice, this list of conditions and the following disclaimer;
   9 # redistributions in binary form must reproduce the above copyright
  10 # notice, this list of conditions and the following disclaimer in the
  11 # documentation and/or other materials provided with the distribution;
  12 # neither the name of the copyright holders nor the names of its
  13 # contributors may be used to endorse or promote products derived from
  14 # this software without specific prior written permission.
  15 #
  16 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27 #
  28 # Authors: Brad Beckmann
  29
  30 import math
  31 import m5
  32 from m5.objects import *
  33 from m5.defines import buildEnv
  34 from Ruby import create_topology
  35
  36 #
  37 # Note: the L1 Cache latency is only used by the sequencer on fast path hits
  38 #
  39 class L1Cache(RubyCache):
  40     latency = 2
  41
  42 #
  43 # Note: the L2 Cache latency is not currently used
  44 #
  45 class L2Cache(RubyCache):
  46     latency = 10
  47
  48 def define_options(parser):
  49     parser.add_option("--l1-retries", type="int", default=1,
  50                       help="Token_CMP: # of l1 retries before going persistent")
  51     parser.add_option("--timeout-latency", type="int", default=300,
  52                       help="Token_CMP: cycles until issuing again");
  53     parser.add_option("--disable-dyn-timeouts", action="store_true",
  54           help="Token_CMP: disable dyanimc timeouts, use fixed latency instead")
  55     parser.add_option("--allow-atomic-migration", action="store_true",
  56           help="allow migratory sharing for atomic only accessed blocks")
  57
  58 def create_system(options, system, piobus, dma_ports, ruby_system):
  59
  60     if buildEnv['PROTOCOL'] != 'MOESI_CMP_token':
  61         panic("This script requires the MOESI_CMP_token protocol to be built.")
  62
  63     #
  64     # number of tokens that the owner passes to requests so that shared blocks can
  65     # respond to read requests
  66     #
  67     n_tokens = options.num_cpus + 1
  68
  69     cpu_sequencers = []
  70
  71     #
  72     # The ruby network creation expects the list of nodes in the system to be
  73     # consistent with the NetDest list.  Therefore the l1 controller nodes must be
  74     # listed before the directory nodes and directory nodes before dma nodes, etc.
  75     #
  76     l1_cntrl_nodes = []
  77     l2_cntrl_nodes = []
  78     dir_cntrl_nodes = []
  79     dma_cntrl_nodes = []
  80
  81     #
  82     # Must create the individual controllers before the network to ensure the
  83     # controller constructors are called before the network constructor
  84     #
  85     l2_bits = int(math.log(options.num_l2caches, 2))
  86     block_size_bits = int(math.log(options.cacheline_size, 2))
  87
  88     for i in xrange(options.num_cpus):
  89         #
  90         # First create the Ruby objects associated with this cpu
  91         #
  92         l1i_cache = L1Cache(size = options.l1i_size,
  93                             assoc = options.l1i_assoc,
  94                             start_index_bit = block_size_bits)
  95         l1d_cache = L1Cache(size = options.l1d_size,
  96                             assoc = options.l1d_assoc,
  97                             start_index_bit = block_size_bits)
  98
  99         l1_cntrl = L1Cache_Controller(version = i,
 100                                       L1Icache = l1i_cache,
 101                                       L1Dcache = l1d_cache,
 102                                       l2_select_num_bits = l2_bits,
 103                                       N_tokens = n_tokens,
 104                                       retry_threshold = \
 105                                         options.l1_retries,
 106                                       fixed_timeout_latency = \
 107                                         options.timeout_latency,
 108                                       dynamic_timeout_enabled = \
 109                                         not options.disable_dyn_timeouts,
 110                                       no_mig_atomic = not \
 111                                         options.allow_atomic_migration,
 112                                       send_evictions = (
 113                                           options.cpu_type == "detailed"),
 114                                       transitions_per_cycle = options.ports,
 115                                       ruby_system = ruby_system)
 116
 117         cpu_seq = RubySequencer(version = i,
 118                                 icache = l1i_cache,
 119                                 dcache = l1d_cache,
 120                                 ruby_system = ruby_system)
 121
 122         l1_cntrl.sequencer = cpu_seq
 123
 124         if piobus != None:
 125             cpu_seq.pio_port = piobus.slave
 126
 127         exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
 128         #
 129         # Add controllers and sequencers to the appropriate lists
 130         #
 131         cpu_sequencers.append(cpu_seq)
 132         l1_cntrl_nodes.append(l1_cntrl)
 133
 134     l2_index_start = block_size_bits + l2_bits
 135
 136     for i in xrange(options.num_l2caches):
 137         #
 138         # First create the Ruby objects associated with this cpu
 139         #
 140         l2_cache = L2Cache(size = options.l2_size,
 141                            assoc = options.l2_assoc,
 142                            start_index_bit = l2_index_start)
 143
 144         l2_cntrl = L2Cache_Controller(version = i,
 145                                       L2cache = l2_cache,
 146                                       N_tokens = n_tokens,
 147                                       transitions_per_cycle = options.ports,
 148                                       ruby_system = ruby_system)
 149
 150         exec("ruby_system.l2_cntrl%d = l2_cntrl" % i)
 151         l2_cntrl_nodes.append(l2_cntrl)
 152
 153     phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
 154     assert(phys_mem_size % options.num_dirs == 0)
 155     mem_module_size = phys_mem_size / options.num_dirs
 156
 157     # Run each of the ruby memory controllers at a ratio of the frequency of
 158     # the ruby system
 159     # clk_divider value is a fix to pass regression.
 160     ruby_system.memctrl_clk_domain = DerivedClockDomain(
 161                                           clk_domain=ruby_system.clk_domain,
 162                                           clk_divider=3)
 163
 164     for i in xrange(options.num_dirs):
 165         #
 166         # Create the Ruby objects associated with the directory controller
 167         #
 168
 169         mem_cntrl = RubyMemoryControl(
 170                               clk_domain = ruby_system.memctrl_clk_domain,
 171                               version = i,
 172                               ruby_system = ruby_system)
 173
 174         dir_size = MemorySize('0B')
 175         dir_size.value = mem_module_size
 176
 177         dir_cntrl = Directory_Controller(version = i,
 178                                          directory = \
 179                                          RubyDirectoryMemory(version = i,
 180                                              use_map = options.use_map,
 181                                              size = dir_size),
 182                                          memBuffer = mem_cntrl,
 183                                          l2_select_num_bits = l2_bits,
 184                                          transitions_per_cycle = options.ports,
 185                                          ruby_system = ruby_system)
 186
 187         exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
 188         dir_cntrl_nodes.append(dir_cntrl)
 189
 190     for i, dma_port in enumerate(dma_ports):
 191         #
 192         # Create the Ruby objects associated with the dma controller
 193         #
 194         dma_seq = DMASequencer(version = i,
 195                                ruby_system = ruby_system)
 196
 197         dma_cntrl = DMA_Controller(version = i,
 198                                    dma_sequencer = dma_seq,
 199                                    transitions_per_cycle = options.ports,
 200                                    ruby_system = ruby_system)
 201
 202         exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
 203         exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
 204         dma_cntrl_nodes.append(dma_cntrl)
 205
 206     all_cntrls = l1_cntrl_nodes + \
 207                  l2_cntrl_nodes + \
 208                  dir_cntrl_nodes + \
 209                  dma_cntrl_nodes
 210
 211     topology = create_topology(all_cntrls, options)
 212
 213     return (cpu_sequencers, dir_cntrl_nodes, topology)