configs/ruby/MOESI_CMP_token.py

   1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
   2 # Copyright (c) 2009 Advanced Micro Devices, Inc.
   3 # All rights reserved.
   4 #
   5 # Redistribution and use in source and binary forms, with or without
   6 # modification, are permitted provided that the following conditions are
   7 # met: redistributions of source code must retain the above copyright
   8 # notice, this list of conditions and the following disclaimer;
   9 # redistributions in binary form must reproduce the above copyright
  10 # notice, this list of conditions and the following disclaimer in the
  11 # documentation and/or other materials provided with the distribution;
  12 # neither the name of the copyright holders nor the names of its
  13 # contributors may be used to endorse or promote products derived from
  14 # this software without specific prior written permission.
  15 #
  16 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27 #
  28 # Authors: Brad Beckmann
  29
  30 import math
  31 import m5
  32 from m5.objects import *
  33 from m5.defines import buildEnv
  34 from m5.util import addToPath
  35
  36 #
  37 # Note: the L1 Cache latency is only used by the sequencer on fast path hits
  38 #
  39 class L1Cache(RubyCache):
  40     latency = 3
  41
  42 #
  43 # Note: the L2 Cache latency is not currently used
  44 #
  45 class L2Cache(RubyCache):
  46     latency = 15
  47
  48 def create_system(options, phys_mem, piobus, dma_devices):
  49
  50     if buildEnv['PROTOCOL'] != 'MOESI_CMP_token':
  51         panic("This script requires the MOESI_CMP_token protocol to be built.")
  52
  53     #
  54     # number of tokens that the owner passes to requests so that shared blocks can
  55     # respond to read requests
  56     #
  57     n_tokens = options.num_cpus + 1
  58
  59     cpu_sequencers = []
  60
  61     #
  62     # The ruby network creation expects the list of nodes in the system to be
  63     # consistent with the NetDest list.  Therefore the l1 controller nodes must be
  64     # listed before the directory nodes and directory nodes before dma nodes, etc.
  65     #
  66     l1_cntrl_nodes = []
  67     l2_cntrl_nodes = []
  68     dir_cntrl_nodes = []
  69     dma_cntrl_nodes = []
  70
  71     #
  72     # Must create the individual controllers before the network to ensure the
  73     # controller constructors are called before the network constructor
  74     #
  75
  76     for i in xrange(options.num_cpus):
  77         #
  78         # First create the Ruby objects associated with this cpu
  79         #
  80         l1i_cache = L1Cache(size = options.l1i_size,
  81                             assoc = options.l1i_assoc)
  82         l1d_cache = L1Cache(size = options.l1d_size,
  83                             assoc = options.l1d_assoc)
  84
  85         cpu_seq = RubySequencer(icache = l1i_cache,
  86                                 dcache = l1d_cache,
  87                                 physMemPort = phys_mem.port,
  88                                 physmem = phys_mem)
  89
  90         if piobus != None:
  91             cpu_seq.pio_port = piobus.port
  92
  93         l1_cntrl = L1Cache_Controller(version = i,
  94                                       sequencer = cpu_seq,
  95                                       L1IcacheMemory = l1i_cache,
  96                                       L1DcacheMemory = l1d_cache,
  97                                       l2_select_num_bits = \
  98                                         math.log(options.num_l2caches, 2),
  99                                       N_tokens = n_tokens)
 100         #
 101         # Add controllers and sequencers to the appropriate lists
 102         #
 103         cpu_sequencers.append(cpu_seq)
 104         l1_cntrl_nodes.append(l1_cntrl)
 105
 106     for i in xrange(options.num_l2caches):
 107         #
 108         # First create the Ruby objects associated with this cpu
 109         #
 110         l2_cache = L2Cache(size = options.l2_size,
 111                            assoc = options.l2_assoc)
 112
 113         l2_cntrl = L2Cache_Controller(version = i,
 114                                       L2cacheMemory = l2_cache,
 115                                       N_tokens = n_tokens)
 116
 117         l2_cntrl_nodes.append(l2_cntrl)
 118
 119     phys_mem_size = long(phys_mem.range.second) - long(phys_mem.range.first) + 1
 120     mem_module_size = phys_mem_size / options.num_dirs
 121
 122     for i in xrange(options.num_dirs):
 123         #
 124         # Create the Ruby objects associated with the directory controller
 125         #
 126
 127         mem_cntrl = RubyMemoryControl(version = i)
 128
 129         dir_size = MemorySize('0B')
 130         dir_size.value = mem_module_size
 131
 132         dir_cntrl = Directory_Controller(version = i,
 133                                          directory = \
 134                                          RubyDirectoryMemory(version = i,
 135                                                              size = dir_size),
 136                                          memBuffer = mem_cntrl,
 137                                          l2_select_num_bits = \
 138                                            math.log(options.num_l2caches, 2))
 139
 140         dir_cntrl_nodes.append(dir_cntrl)
 141
 142     for i, dma_device in enumerate(dma_devices):
 143         #
 144         # Create the Ruby objects associated with the dma controller
 145         #
 146         dma_seq = DMASequencer(version = i,
 147                                physMemPort = phys_mem.port,
 148                                physmem = phys_mem)
 149
 150         dma_cntrl = DMA_Controller(version = i,
 151                                    dma_sequencer = dma_seq)
 152
 153         dma_cntrl.dma_sequencer.port = dma_device.dma
 154         dma_cntrl_nodes.append(dma_cntrl)
 155
 156     all_cntrls = l1_cntrl_nodes + \
 157                  l2_cntrl_nodes + \
 158                  dir_cntrl_nodes + \
 159                  dma_cntrl_nodes
 160
 161     return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)