configs/ruby/MOESI_hammer.py

   1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
   2 # Copyright (c) 2009 Advanced Micro Devices, Inc.
   3 # All rights reserved.
   4 #
   5 # Redistribution and use in source and binary forms, with or without
   6 # modification, are permitted provided that the following conditions are
   7 # met: redistributions of source code must retain the above copyright
   8 # notice, this list of conditions and the following disclaimer;
   9 # redistributions in binary form must reproduce the above copyright
  10 # notice, this list of conditions and the following disclaimer in the
  11 # documentation and/or other materials provided with the distribution;
  12 # neither the name of the copyright holders nor the names of its
  13 # contributors may be used to endorse or promote products derived from
  14 # this software without specific prior written permission.
  15 #
  16 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27
  28 import math
  29 import m5
  30 from m5.objects import *
  31 from m5.defines import buildEnv
  32 from Ruby import create_topology, create_directories
  33 from Ruby import send_evicts
  34 from common import FileSystemConfig
  35
  36 #
  37 # Declare caches used by the protocol
  38 #
  39 class L1Cache(RubyCache): pass
  40 class L2Cache(RubyCache): pass
  41 #
  42 # Probe filter is a cache
  43 #
  44 class ProbeFilter(RubyCache): pass
  45
  46 def define_options(parser):
  47     parser.add_option("--allow-atomic-migration", action="store_true",
  48           help="allow migratory sharing for atomic only accessed blocks")
  49     parser.add_option("--pf-on", action="store_true",
  50           help="Hammer: enable Probe Filter")
  51     parser.add_option("--dir-on", action="store_true",
  52           help="Hammer: enable Full-bit Directory")
  53
  54 def create_system(options, full_system, system, dma_ports, bootmem,
  55                   ruby_system):
  56
  57     if buildEnv['PROTOCOL'] != 'MOESI_hammer':
  58         panic("This script requires the MOESI_hammer protocol to be built.")
  59
  60     cpu_sequencers = []
  61
  62     #
  63     # The ruby network creation expects the list of nodes in the system to be
  64     # consistent with the NetDest list.  Therefore the l1 controller nodes must be
  65     # listed before the directory nodes and directory nodes before dma nodes, etc.
  66     #
  67     l1_cntrl_nodes = []
  68     dma_cntrl_nodes = []
  69
  70     #
  71     # Must create the individual controllers before the network to ensure the
  72     # controller constructors are called before the network constructor
  73     #
  74     block_size_bits = int(math.log(options.cacheline_size, 2))
  75
  76     for i in range(options.num_cpus):
  77         #
  78         # First create the Ruby objects associated with this cpu
  79         #
  80         l1i_cache = L1Cache(size = options.l1i_size,
  81                             assoc = options.l1i_assoc,
  82                             start_index_bit = block_size_bits,
  83                             is_icache = True)
  84         l1d_cache = L1Cache(size = options.l1d_size,
  85                             assoc = options.l1d_assoc,
  86                             start_index_bit = block_size_bits)
  87         l2_cache = L2Cache(size = options.l2_size,
  88                            assoc = options.l2_assoc,
  89                            start_index_bit = block_size_bits)
  90
  91         # the ruby random tester reuses num_cpus to specify the
  92         # number of cpu ports connected to the tester object, which
  93         # is stored in system.cpu. because there is only ever one
  94         # tester object, num_cpus is not necessarily equal to the
  95         # size of system.cpu; therefore if len(system.cpu) == 1
  96         # we use system.cpu[0] to set the clk_domain, thereby ensuring
  97         # we don't index off the end of the cpu list.
  98         if len(system.cpu) == 1:
  99             clk_domain = system.cpu[0].clk_domain
 100         else:
 101             clk_domain = system.cpu[i].clk_domain
 102
 103         l1_cntrl = L1Cache_Controller(version=i, L1Icache=l1i_cache,
 104                                       L1Dcache=l1d_cache, L2cache=l2_cache,
 105                                       no_mig_atomic=not \
 106                                       options.allow_atomic_migration,
 107                                       send_evictions=send_evicts(options),
 108                                       transitions_per_cycle=options.ports,
 109                                       clk_domain=clk_domain,
 110                                       ruby_system=ruby_system)
 111
 112         cpu_seq = RubySequencer(version=i, icache=l1i_cache,
 113                                 dcache=l1d_cache,clk_domain=clk_domain,
 114                                 ruby_system=ruby_system)
 115
 116         l1_cntrl.sequencer = cpu_seq
 117         if options.recycle_latency:
 118             l1_cntrl.recycle_latency = options.recycle_latency
 119
 120         exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
 121
 122         # Add controllers and sequencers to the appropriate lists
 123         cpu_sequencers.append(cpu_seq)
 124         l1_cntrl_nodes.append(l1_cntrl)
 125
 126         # Connect the L1 controller and the network
 127         # Connect the buffers from the controller to network
 128         l1_cntrl.requestFromCache = MessageBuffer()
 129         l1_cntrl.requestFromCache.master = ruby_system.network.slave
 130         l1_cntrl.responseFromCache = MessageBuffer()
 131         l1_cntrl.responseFromCache.master = ruby_system.network.slave
 132         l1_cntrl.unblockFromCache = MessageBuffer()
 133         l1_cntrl.unblockFromCache.master = ruby_system.network.slave
 134
 135         l1_cntrl.triggerQueue = MessageBuffer()
 136
 137         # Connect the buffers from the network to the controller
 138         l1_cntrl.mandatoryQueue = MessageBuffer()
 139         l1_cntrl.forwardToCache = MessageBuffer()
 140         l1_cntrl.forwardToCache.slave = ruby_system.network.master
 141         l1_cntrl.responseToCache = MessageBuffer()
 142         l1_cntrl.responseToCache.slave = ruby_system.network.master
 143
 144
 145     #
 146     # determine size and index bits for probe filter
 147     # By default, the probe filter size is configured to be twice the
 148     # size of the L2 cache.
 149     #
 150     pf_size = MemorySize(options.l2_size)
 151     pf_size.value = pf_size.value * 2
 152     dir_bits = int(math.log(options.num_dirs, 2))
 153     pf_bits = int(math.log(pf_size.value, 2))
 154     if options.numa_high_bit:
 155         if options.pf_on or options.dir_on:
 156             # if numa high bit explicitly set, make sure it does not overlap
 157             # with the probe filter index
 158             assert(options.numa_high_bit - dir_bits > pf_bits)
 159
 160         # set the probe filter start bit to just above the block offset
 161         pf_start_bit = block_size_bits
 162     else:
 163         if dir_bits > 0:
 164             pf_start_bit = dir_bits + block_size_bits - 1
 165         else:
 166             pf_start_bit = block_size_bits
 167
 168     # Run each of the ruby memory controllers at a ratio of the frequency of
 169     # the ruby system
 170     # clk_divider value is a fix to pass regression.
 171     ruby_system.memctrl_clk_domain = DerivedClockDomain(
 172                                           clk_domain=ruby_system.clk_domain,
 173                                           clk_divider=3)
 174
 175     mem_dir_cntrl_nodes, rom_dir_cntrl_node = create_directories(
 176         options, bootmem, ruby_system, system)
 177     dir_cntrl_nodes = mem_dir_cntrl_nodes[:]
 178     if rom_dir_cntrl_node is not None:
 179         dir_cntrl_nodes.append(rom_dir_cntrl_node)
 180     for dir_cntrl in dir_cntrl_nodes:
 181         pf = ProbeFilter(size = pf_size, assoc = 4,
 182                          start_index_bit = pf_start_bit)
 183
 184         dir_cntrl.probeFilter = pf
 185         dir_cntrl.probe_filter_enabled = options.pf_on
 186         dir_cntrl.full_bit_dir_enabled = options.dir_on
 187
 188         if options.recycle_latency:
 189             dir_cntrl.recycle_latency = options.recycle_latency
 190
 191         # Connect the directory controller to the network
 192         dir_cntrl.forwardFromDir = MessageBuffer()
 193         dir_cntrl.forwardFromDir.master = ruby_system.network.slave
 194         dir_cntrl.responseFromDir = MessageBuffer()
 195         dir_cntrl.responseFromDir.master = ruby_system.network.slave
 196         dir_cntrl.dmaResponseFromDir = MessageBuffer(ordered = True)
 197         dir_cntrl.dmaResponseFromDir.master = ruby_system.network.slave
 198
 199         dir_cntrl.triggerQueue = MessageBuffer(ordered = True)
 200
 201         dir_cntrl.unblockToDir = MessageBuffer()
 202         dir_cntrl.unblockToDir.slave = ruby_system.network.master
 203         dir_cntrl.responseToDir = MessageBuffer()
 204         dir_cntrl.responseToDir.slave = ruby_system.network.master
 205         dir_cntrl.requestToDir = MessageBuffer()
 206         dir_cntrl.requestToDir.slave = ruby_system.network.master
 207         dir_cntrl.dmaRequestToDir = MessageBuffer(ordered = True)
 208         dir_cntrl.dmaRequestToDir.slave = ruby_system.network.master
 209         dir_cntrl.requestToMemory = MessageBuffer()
 210         dir_cntrl.responseFromMemory = MessageBuffer()
 211
 212
 213     for i, dma_port in enumerate(dma_ports):
 214         #
 215         # Create the Ruby objects associated with the dma controller
 216         #
 217         dma_seq = DMASequencer(version = i,
 218                                ruby_system = ruby_system,
 219                                slave = dma_port)
 220
 221         dma_cntrl = DMA_Controller(version = i,
 222                                    dma_sequencer = dma_seq,
 223                                    transitions_per_cycle = options.ports,
 224                                    ruby_system = ruby_system)
 225
 226         exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
 227         dma_cntrl_nodes.append(dma_cntrl)
 228
 229         if options.recycle_latency:
 230             dma_cntrl.recycle_latency = options.recycle_latency
 231
 232         # Connect the dma controller to the network
 233         dma_cntrl.responseFromDir = MessageBuffer(ordered = True)
 234         dma_cntrl.responseFromDir.slave = ruby_system.network.master
 235         dma_cntrl.requestToDir = MessageBuffer()
 236         dma_cntrl.requestToDir.master = ruby_system.network.slave
 237         dma_cntrl.mandatoryQueue = MessageBuffer()
 238
 239     all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
 240
 241     # Create the io controller and the sequencer
 242     if full_system:
 243         io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system)
 244         ruby_system._io_port = io_seq
 245         io_controller = DMA_Controller(version = len(dma_ports),
 246                                        dma_sequencer = io_seq,
 247                                        ruby_system = ruby_system)
 248         ruby_system.io_controller = io_controller
 249
 250         # Connect the dma controller to the network
 251         io_controller.responseFromDir = MessageBuffer(ordered = True)
 252         io_controller.responseFromDir.slave = ruby_system.network.master
 253         io_controller.requestToDir = MessageBuffer()
 254         io_controller.requestToDir.master = ruby_system.network.slave
 255         io_controller.mandatoryQueue = MessageBuffer()
 256
 257         all_cntrls = all_cntrls + [io_controller]
 258     # Register configuration with filesystem
 259     else:
 260         for i in xrange(options.num_cpus):
 261             FileSystemConfig.register_cpu(physical_package_id = 0,
 262                                           core_siblings = [],
 263                                           core_id = i,
 264                                           thread_siblings = [])
 265
 266             FileSystemConfig.register_cache(level = 1,
 267                                             idu_type = 'Instruction',
 268                                             size = options.l1i_size,
 269                                             line_size = options.cacheline_size,
 270                                             assoc = options.l1i_assoc,
 271                                             cpus = [i])
 272             FileSystemConfig.register_cache(level = 1,
 273                                             idu_type = 'Data',
 274                                             size = options.l1d_size,
 275                                             line_size = options.cacheline_size,
 276                                             assoc = options.l1d_assoc,
 277                                             cpus = [i])
 278
 279             FileSystemConfig.register_cache(level = 2,
 280                                             idu_type = 'Unified',
 281                                             size = options.l2_size,
 282                                             line_size = options.cacheline_size,
 283                                             assoc = options.l2_assoc,
 284                                             cpus = [i])
 285
 286     ruby_system.network.number_of_virtual_networks = 6
 287     topology = create_topology(all_cntrls, options)
 288     return (cpu_sequencers, mem_dir_cntrl_nodes, topology)