configs/ruby/MOESI_hammer.py

   1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
   2 # Copyright (c) 2009 Advanced Micro Devices, Inc.
   3 # All rights reserved.
   4 #
   5 # Redistribution and use in source and binary forms, with or without
   6 # modification, are permitted provided that the following conditions are
   7 # met: redistributions of source code must retain the above copyright
   8 # notice, this list of conditions and the following disclaimer;
   9 # redistributions in binary form must reproduce the above copyright
  10 # notice, this list of conditions and the following disclaimer in the
  11 # documentation and/or other materials provided with the distribution;
  12 # neither the name of the copyright holders nor the names of its
  13 # contributors may be used to endorse or promote products derived from
  14 # this software without specific prior written permission.
  15 #
  16 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27 #
  28 # Authors: Brad Beckmann
  29
  30 import math
  31 import m5
  32 from m5.objects import *
  33 from m5.defines import buildEnv
  34
  35 #
  36 # Note: the L1 Cache latency is only used by the sequencer on fast path hits
  37 #
  38 class L1Cache(RubyCache):
  39     latency = 2
  40
  41 #
  42 # Note: the L2 Cache latency is not currently used
  43 #
  44 class L2Cache(RubyCache):
  45     latency = 10
  46
  47 #
  48 # Probe filter is a cache, latency is not used
  49 #
  50 class ProbeFilter(RubyCache):
  51     latency = 1
  52
  53 def define_options(parser):
  54     parser.add_option("--allow-atomic-migration", action="store_true",
  55           help="allow migratory sharing for atomic only accessed blocks")
  56     parser.add_option("--pf-on", action="store_true",
  57           help="Hammer: enable Probe Filter")
  58     parser.add_option("--dir-on", action="store_true",
  59           help="Hammer: enable Full-bit Directory")
  60
  61 def create_system(options, system, piobus, dma_devices, ruby_system):
  62
  63     if buildEnv['PROTOCOL'] != 'MOESI_hammer':
  64         panic("This script requires the MOESI_hammer protocol to be built.")
  65
  66     cpu_sequencers = []
  67
  68     #
  69     # The ruby network creation expects the list of nodes in the system to be
  70     # consistent with the NetDest list.  Therefore the l1 controller nodes must be
  71     # listed before the directory nodes and directory nodes before dma nodes, etc.
  72     #
  73     l1_cntrl_nodes = []
  74     dir_cntrl_nodes = []
  75     dma_cntrl_nodes = []
  76
  77     #
  78     # Must create the individual controllers before the network to ensure the
  79     # controller constructors are called before the network constructor
  80     #
  81     block_size_bits = int(math.log(options.cacheline_size, 2))
  82
  83     cntrl_count = 0
  84
  85     for i in xrange(options.num_cpus):
  86         #
  87         # First create the Ruby objects associated with this cpu
  88         #
  89         l1i_cache = L1Cache(size = options.l1i_size,
  90                             assoc = options.l1i_assoc,
  91                             start_index_bit = block_size_bits)
  92         l1d_cache = L1Cache(size = options.l1d_size,
  93                             assoc = options.l1d_assoc,
  94                             start_index_bit = block_size_bits)
  95         l2_cache = L2Cache(size = options.l2_size,
  96                            assoc = options.l2_assoc,
  97                            start_index_bit = block_size_bits)
  98
  99         l1_cntrl = L1Cache_Controller(version = i,
 100                                       cntrl_id = cntrl_count,
 101                                       L1IcacheMemory = l1i_cache,
 102                                       L1DcacheMemory = l1d_cache,
 103                                       L2cacheMemory = l2_cache,
 104                                       no_mig_atomic = not \
 105                                         options.allow_atomic_migration,
 106                                       ruby_system = ruby_system)
 107
 108         cpu_seq = RubySequencer(version = i,
 109                                 icache = l1i_cache,
 110                                 dcache = l1d_cache,
 111                                 physMemPort = system.physmem.port,
 112                                 physmem = system.physmem,
 113                                 ruby_system = ruby_system)
 114
 115         l1_cntrl.sequencer = cpu_seq
 116
 117         if piobus != None:
 118             cpu_seq.pio_port = piobus.port
 119
 120         if options.recycle_latency:
 121             l1_cntrl.recycle_latency = options.recycle_latency
 122
 123         exec("system.l1_cntrl%d = l1_cntrl" % i)
 124         #
 125         # Add controllers and sequencers to the appropriate lists
 126         #
 127         cpu_sequencers.append(cpu_seq)
 128         l1_cntrl_nodes.append(l1_cntrl)
 129
 130         cntrl_count += 1
 131
 132     phys_mem_size = long(system.physmem.range.second) - \
 133                       long(system.physmem.range.first) + 1
 134     mem_module_size = phys_mem_size / options.num_dirs
 135
 136     #
 137     # determine size and index bits for probe filter
 138     # By default, the probe filter size is configured to be twice the
 139     # size of the L2 cache.
 140     #
 141     pf_size = MemorySize(options.l2_size)
 142     pf_size.value = pf_size.value * 2
 143     dir_bits = int(math.log(options.num_dirs, 2))
 144     pf_bits = int(math.log(pf_size.value, 2))
 145     if options.numa_high_bit:
 146         if options.numa_high_bit > 0:
 147             # if numa high bit explicitly set, make sure it does not overlap
 148             # with the probe filter index
 149             assert(options.numa_high_bit - dir_bits > pf_bits)
 150
 151         # set the probe filter start bit to just above the block offset
 152         pf_start_bit = 6
 153     else:
 154         if dir_bits > 0:
 155             pf_start_bit = dir_bits + 5
 156         else:
 157             pf_start_bit = 6
 158
 159     for i in xrange(options.num_dirs):
 160         #
 161         # Create the Ruby objects associated with the directory controller
 162         #
 163
 164         mem_cntrl = RubyMemoryControl(version = i)
 165
 166         dir_size = MemorySize('0B')
 167         dir_size.value = mem_module_size
 168
 169         pf = ProbeFilter(size = pf_size, assoc = 4,
 170                          start_index_bit = pf_start_bit)
 171
 172         dir_cntrl = Directory_Controller(version = i,
 173                                          cntrl_id = cntrl_count,
 174                                          directory = \
 175                                          RubyDirectoryMemory( \
 176                                                     version = i,
 177                                                     size = dir_size,
 178                                                     use_map = options.use_map,
 179                                                     map_levels = \
 180                                                     options.map_levels,
 181                                                     numa_high_bit = \
 182                                                       options.numa_high_bit),
 183                                          probeFilter = pf,
 184                                          memBuffer = mem_cntrl,
 185                                          probe_filter_enabled = options.pf_on,
 186                                          full_bit_dir_enabled = options.dir_on,
 187                                          ruby_system = ruby_system)
 188
 189         if options.recycle_latency:
 190             dir_cntrl.recycle_latency = options.recycle_latency
 191
 192         exec("system.dir_cntrl%d = dir_cntrl" % i)
 193         dir_cntrl_nodes.append(dir_cntrl)
 194
 195         cntrl_count += 1
 196
 197     for i, dma_device in enumerate(dma_devices):
 198         #
 199         # Create the Ruby objects associated with the dma controller
 200         #
 201         dma_seq = DMASequencer(version = i,
 202                                physMemPort = system.physmem.port,
 203                                physmem = system.physmem)
 204
 205         dma_cntrl = DMA_Controller(version = i,
 206                                    cntrl_id = cntrl_count,
 207                                    dma_sequencer = dma_seq)
 208
 209         exec("system.dma_cntrl%d = dma_cntrl" % i)
 210         if dma_device.type == 'MemTest':
 211             exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i)
 212         else:
 213             exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i)
 214         dma_cntrl_nodes.append(dma_cntrl)
 215
 216         if options.recycle_latency:
 217             dma_cntrl.recycle_latency = options.recycle_latency
 218
 219         cntrl_count += 1
 220
 221     all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
 222
 223     return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)