configs/ruby/Network_test.py

   1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
   2 # Copyright (c) 2009 Advanced Micro Devices, Inc.
   3 # All rights reserved.
   4 #
   5 # Redistribution and use in source and binary forms, with or without
   6 # modification, are permitted provided that the following conditions are
   7 # met: redistributions of source code must retain the above copyright
   8 # notice, this list of conditions and the following disclaimer;
   9 # redistributions in binary form must reproduce the above copyright
  10 # notice, this list of conditions and the following disclaimer in the
  11 # documentation and/or other materials provided with the distribution;
  12 # neither the name of the copyright holders nor the names of its
  13 # contributors may be used to endorse or promote products derived from
  14 # this software without specific prior written permission.
  15 #
  16 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27 #
  28 # Authors: Brad Beckmann
  29
  30 import m5
  31 from m5.objects import *
  32 from m5.defines import buildEnv
  33 from m5.util import addToPath
  34
  35 #
  36 # Note: the cache latency is only used by the sequencer on fast path hits
  37 #
  38 class Cache(RubyCache):
  39     latency = 3
  40
  41 def define_options(parser):
  42     return
  43
  44 def create_system(options, system, piobus, dma_devices, ruby_system):
  45
  46     if buildEnv['PROTOCOL'] != 'Network_test':
  47         panic("This script requires the Network_test protocol to be built.")
  48
  49     cpu_sequencers = []
  50
  51     #
  52     # The Garnet tester protocol does not support fs nor dma
  53     #
  54     assert(piobus == None)
  55     assert(dma_devices == [])
  56
  57     #
  58     # The ruby network creation expects the list of nodes in the system to be
  59     # consistent with the NetDest list.  Therefore the l1 controller nodes must be
  60     # listed before the directory nodes and directory nodes before dma nodes, etc.
  61     #
  62     l1_cntrl_nodes = []
  63     dir_cntrl_nodes = []
  64
  65     #
  66     # Must create the individual controllers before the network to ensure the
  67     # controller constructors are called before the network constructor
  68     #
  69
  70     cntrl_count = 0
  71
  72     for i in xrange(options.num_cpus):
  73         #
  74         # First create the Ruby objects associated with this cpu
  75         # Only one cache exists for this protocol, so by default use the L1D
  76         # config parameters.
  77         #
  78         cache = Cache(size = options.l1d_size,
  79                       assoc = options.l1d_assoc)
  80
  81         #
  82         # Only one unified L1 cache exists.  Can cache instructions and data.
  83         #
  84         l1_cntrl = L1Cache_Controller(version = i,
  85                                       cntrl_id = cntrl_count,
  86                                       cacheMemory = cache,
  87                                       ruby_system = ruby_system)
  88
  89         cpu_seq = RubySequencer(icache = cache,
  90                                 dcache = cache,
  91                                 physMemPort = system.physmem.port,
  92                                 physmem = system.physmem,
  93                                 using_network_tester = True,
  94                                 ruby_system = ruby_system)
  95
  96         l1_cntrl.sequencer = cpu_seq
  97
  98         if piobus != None:
  99             cpu_seq.pio_port = piobus.port
 100
 101         exec("system.l1_cntrl%d = l1_cntrl" % i)
 102         #
 103         # Add controllers and sequencers to the appropriate lists
 104         #
 105         cpu_sequencers.append(cpu_seq)
 106         l1_cntrl_nodes.append(l1_cntrl)
 107
 108         cntrl_count += 1
 109
 110     phys_mem_size = long(system.physmem.range.second) - \
 111                       long(system.physmem.range.first) + 1
 112     mem_module_size = phys_mem_size / options.num_dirs
 113
 114     for i in xrange(options.num_dirs):
 115         #
 116         # Create the Ruby objects associated with the directory controller
 117         #
 118
 119         mem_cntrl = RubyMemoryControl(version = i)
 120
 121         dir_size = MemorySize('0B')
 122         dir_size.value = mem_module_size
 123
 124         dir_cntrl = Directory_Controller(version = i,
 125                                          cntrl_id = cntrl_count,
 126                                          directory = \
 127                                          RubyDirectoryMemory(version = i,
 128                                                              size = dir_size),
 129                                          memBuffer = mem_cntrl,
 130                                          ruby_system = ruby_system)
 131
 132         exec("system.dir_cntrl%d = dir_cntrl" % i)
 133         dir_cntrl_nodes.append(dir_cntrl)
 134
 135         cntrl_count += 1
 136
 137     all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes
 138
 139     return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)