1 # Copyright (c) 2012, 2017-2018 ARM Limited
4 # The license below extends only to copyright in the software and shall
5 # not be construed as granting a license to any other intellectual
6 # property including but not limited to intellectual property relating
7 # to a hardware implementation of the functionality of the software
8 # licensed hereunder. You may use the software subject to the license
9 # terms below provided that you ensure that this notice is replicated
10 # unmodified and in its entirety in all distributions of the software,
11 # modified or unmodified, in source code or in binary form.
13 # Copyright (c) 2006-2007 The Regents of The University of Michigan
14 # Copyright (c) 2009 Advanced Micro Devices, Inc.
15 # All rights reserved.
17 # Redistribution and use in source and binary forms, with or without
18 # modification, are permitted provided that the following conditions are
19 # met: redistributions of source code must retain the above copyright
20 # notice, this list of conditions and the following disclaimer;
21 # redistributions in binary form must reproduce the above copyright
22 # notice, this list of conditions and the following disclaimer in the
23 # documentation and/or other materials provided with the distribution;
24 # neither the name of the copyright holders nor the names of its
25 # contributors may be used to endorse or promote products derived from
26 # this software without specific prior written permission.
28 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 # Authors: Brad Beckmann
42 from __future__
import print_function
46 from m5
.objects
import *
47 from m5
.defines
import buildEnv
48 from m5
.util
import addToPath
, fatal
50 from common
import MemConfig
52 from topologies
import *
53 from network
import Network
55 def define_options(parser
):
56 # By default, ruby uses the simple timing cpu
57 parser
.set_defaults(cpu_type
="TimingSimpleCPU")
59 parser
.add_option("--ruby-clock", action
="store", type="string",
61 help="Clock for blocks running at Ruby system's speed")
63 parser
.add_option("--access-backing-store", action
="store_true", default
=False,
64 help="Should ruby maintain a second copy of memory")
66 # Options related to cache structure
67 parser
.add_option("--ports", action
="store", type="int", default
=4,
68 help="used of transitions per cycle which is a proxy \
69 for the number of ports.")
71 # network options are in network/Network.py
73 # ruby mapping options
74 parser
.add_option("--numa-high-bit", type="int", default
=0,
75 help="high order address bit to use for numa mapping. " \
76 "0 = highest bit, not specified = lowest bit")
78 parser
.add_option("--recycle-latency", type="int", default
=10,
79 help="Recycle latency for ruby controller input buffers")
81 protocol
= buildEnv
['PROTOCOL']
82 exec "import %s" % protocol
83 eval("%s.define_options(parser)" % protocol
)
84 Network
.define_options(parser
)
86 def setup_memory_controllers(system
, ruby
, dir_cntrls
, options
):
87 ruby
.block_size_bytes
= options
.cacheline_size
88 ruby
.memory_size_bits
= 48
94 if options
.numa_high_bit
:
95 dir_bits
= int(math
.log(options
.num_dirs
, 2))
96 intlv_size
= 2 ** (options
.numa_high_bit
- dir_bits
+ 1)
98 # if the numa_bit is not specified, set the directory bits as the
99 # lowest bits above the block offset bits
100 intlv_size
= options
.cacheline_size
102 # Sets bits to be used for interleaving. Creates memory controllers
103 # attached to a directory controller. A separate controller is created
104 # for each address range as the abstract memory can handle only one
105 # contiguous address range as of now.
106 for dir_cntrl
in dir_cntrls
:
108 if len(system
.mem_ranges
) > 1:
110 crossbars
.append(crossbar
)
111 dir_cntrl
.memory
= crossbar
.slave
114 for r
in system
.mem_ranges
:
115 mem_ctrl
= MemConfig
.create_mem_ctrl(
116 MemConfig
.get(options
.mem_type
), r
, index
, options
.num_dirs
,
117 int(math
.log(options
.num_dirs
, 2)), intlv_size
)
119 if options
.access_backing_store
:
120 mem_ctrl
.kvm_map
=False
122 mem_ctrls
.append(mem_ctrl
)
123 dir_ranges
.append(mem_ctrl
.range)
126 mem_ctrl
.port
= crossbar
.master
128 mem_ctrl
.port
= dir_cntrl
.memory
131 dir_cntrl
.addr_ranges
= dir_ranges
133 system
.mem_ctrls
= mem_ctrls
135 if len(crossbars
) > 0:
136 ruby
.crossbars
= crossbars
139 def create_topology(controllers
, options
):
140 """ Called from create_system in configs/ruby/<protocol>.py
141 Must return an object which is a subclass of BaseTopology
142 found in configs/topologies/BaseTopology.py
143 This is a wrapper for the legacy topologies.
145 exec "import topologies.%s as Topo" % options
.topology
146 topology
= eval("Topo.%s(controllers)" % options
.topology
)
149 def create_system(options
, full_system
, system
, piobus
= None, dma_ports
= [],
152 system
.ruby
= RubySystem()
155 # Create the network object
156 (network
, IntLinkClass
, ExtLinkClass
, RouterClass
, InterfaceClass
) = \
157 Network
.create_network(options
, ruby
)
158 ruby
.network
= network
160 protocol
= buildEnv
['PROTOCOL']
161 exec "import %s" % protocol
163 (cpu_sequencers
, dir_cntrls
, topology
) = \
164 eval("%s.create_system(options, full_system, system, dma_ports,\
168 print("Error: could not create sytem for ruby protocol %s" % protocol
)
171 # Create the network topology
172 topology
.makeTopology(options
, network
, IntLinkClass
, ExtLinkClass
,
175 # Initialize network based on topology
176 Network
.init_network(options
, network
, InterfaceClass
)
178 # Create a port proxy for connecting the system port. This is
179 # independent of the protocol and kept in the protocol-agnostic
181 sys_port_proxy
= RubyPortProxy(ruby_system
= ruby
)
182 if piobus
is not None:
183 sys_port_proxy
.pio_master_port
= piobus
.slave
185 # Give the system port proxy a SimObject parent without creating a
186 # full-fledged controller
187 system
.sys_port_proxy
= sys_port_proxy
189 # Connect the system port for loading of binaries etc
190 system
.system_port
= system
.sys_port_proxy
.slave
192 setup_memory_controllers(system
, ruby
, dir_cntrls
, options
)
194 # Connect the cpu sequencers and the piobus
196 for cpu_seq
in cpu_sequencers
:
197 cpu_seq
.pio_master_port
= piobus
.slave
198 cpu_seq
.mem_master_port
= piobus
.slave
200 if buildEnv
['TARGET_ISA'] == "x86":
201 cpu_seq
.pio_slave_port
= piobus
.master
203 ruby
.number_of_virtual_networks
= ruby
.network
.number_of_virtual_networks
204 ruby
._cpu
_ports
= cpu_sequencers
205 ruby
.num_of_sequencers
= len(cpu_sequencers
)
207 # Create a backing copy of physical memory in case required
208 if options
.access_backing_store
:
209 ruby
.access_backing_store
= True
210 ruby
.phys_mem
= SimpleMemory(range=system
.mem_ranges
[0],
213 def create_directories(options
, bootmem
, ruby_system
, system
):
215 for i
in xrange(options
.num_dirs
):
216 dir_cntrl
= Directory_Controller()
217 dir_cntrl
.version
= i
218 dir_cntrl
.directory
= RubyDirectoryMemory()
219 dir_cntrl
.ruby_system
= ruby_system
221 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i
)
222 dir_cntrl_nodes
.append(dir_cntrl
)
224 if bootmem
is not None:
225 rom_dir_cntrl
= Directory_Controller()
226 rom_dir_cntrl
.directory
= RubyDirectoryMemory()
227 rom_dir_cntrl
.ruby_system
= ruby_system
228 rom_dir_cntrl
.version
= i
+ 1
229 rom_dir_cntrl
.memory
= bootmem
.port
230 rom_dir_cntrl
.addr_ranges
= bootmem
.range
231 return (dir_cntrl_nodes
, rom_dir_cntrl
)
233 return (dir_cntrl_nodes
, None)
235 def send_evicts(options
):
236 # currently, 2 scenarios warrant forwarding evictions to the CPU:
237 # 1. The O3 model must keep the LSQ coherent with the caches
238 # 2. The x86 mwait instruction is built on top of coherence invalidations
239 # 3. The local exclusive monitor in ARM systems
240 if options
.cpu_type
== "DerivO3CPU" or \
241 buildEnv
['TARGET_ISA'] in ('x86', 'arm'):