configs/ruby/Ruby.py

   1 # Copyright (c) 2012, 2017-2018 ARM Limited
   2 # All rights reserved.
   3 #
   4 # The license below extends only to copyright in the software and shall
   5 # not be construed as granting a license to any other intellectual
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  11 # modified or unmodified, in source code or in binary form.
  12 #
  13 # Copyright (c) 2006-2007 The Regents of The University of Michigan
  14 # Copyright (c) 2009 Advanced Micro Devices, Inc.
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  39
  40 from __future__ import print_function
  41
  42 import math
  43 import m5
  44 from m5.objects import *
  45 from m5.defines import buildEnv
  46 from m5.util import addToPath, fatal
  47
  48 addToPath('../')
  49
  50 from common import ObjectList
  51 from common import MemConfig
  52 from common import FileSystemConfig
  53
  54 from topologies import *
  55 from network import Network
  56
  57 def define_options(parser):
  58     # By default, ruby uses the simple timing cpu
  59     parser.set_defaults(cpu_type="TimingSimpleCPU")
  60
  61     parser.add_option("--ruby-clock", action="store", type="string",
  62                       default='2GHz',
  63                       help="Clock for blocks running at Ruby system's speed")
  64
  65     parser.add_option("--access-backing-store", action="store_true", default=False,
  66                       help="Should ruby maintain a second copy of memory")
  67
  68     # Options related to cache structure
  69     parser.add_option("--ports", action="store", type="int", default=4,
  70                       help="used of transitions per cycle which is a proxy \
  71                             for the number of ports.")
  72
  73     # network options are in network/Network.py
  74
  75     # ruby mapping options
  76     parser.add_option("--numa-high-bit", type="int", default=0,
  77                       help="high order address bit to use for numa mapping. " \
  78                            "0 = highest bit, not specified = lowest bit")
  79     parser.add_option("--interleaving-bits", type="int", default=0,
  80                       help="number of bits to specify interleaving " \
  81                            "in directory, memory controllers and caches. "
  82                            "0 = not specified")
  83     parser.add_option("--xor-low-bit", type="int", default=20,
  84                       help="hashing bit for channel selection" \
  85                            "see MemConfig for explanation of the default"\
  86                            "parameter. If set to 0, xor_high_bit is also"\
  87                            "set to 0.")
  88
  89     parser.add_option("--recycle-latency", type="int", default=10,
  90                       help="Recycle latency for ruby controller input buffers")
  91
  92     protocol = buildEnv['PROTOCOL']
  93     exec("from . import %s" % protocol)
  94     eval("%s.define_options(parser)" % protocol)
  95     Network.define_options(parser)
  96
  97 def setup_memory_controllers(system, ruby, dir_cntrls, options):
  98     if (options.numa_high_bit):
  99         block_size_bits = options.numa_high_bit + 1 - \
 100                           int(math.log(options.num_dirs, 2))
 101         ruby.block_size_bytes = 2 ** (block_size_bits)
 102     else:
 103         ruby.block_size_bytes = options.cacheline_size
 104
 105     ruby.memory_size_bits = 48
 106
 107     index = 0
 108     mem_ctrls = []
 109     crossbars = []
 110
 111     if options.numa_high_bit:
 112         dir_bits = int(math.log(options.num_dirs, 2))
 113         intlv_size = 2 ** (options.numa_high_bit - dir_bits + 1)
 114     else:
 115         # if the numa_bit is not specified, set the directory bits as the
 116         # lowest bits above the block offset bits
 117         intlv_size = options.cacheline_size
 118
 119     # Sets bits to be used for interleaving.  Creates memory controllers
 120     # attached to a directory controller.  A separate controller is created
 121     # for each address range as the abstract memory can handle only one
 122     # contiguous address range as of now.
 123     for dir_cntrl in dir_cntrls:
 124         crossbar = None
 125         if len(system.mem_ranges) > 1:
 126             crossbar = IOXBar()
 127             crossbars.append(crossbar)
 128             dir_cntrl.memory = crossbar.slave
 129
 130         dir_ranges = []
 131         for r in system.mem_ranges:
 132             mem_type = ObjectList.mem_list.get(options.mem_type)
 133             mem_ctrl = MemConfig.create_mem_ctrl(mem_type, r, index,
 134                 options.num_dirs, int(math.log(options.num_dirs, 2)),
 135                 intlv_size, options.xor_low_bit)
 136
 137             if options.access_backing_store:
 138                 mem_ctrl.kvm_map=False
 139
 140             mem_ctrls.append(mem_ctrl)
 141             dir_ranges.append(mem_ctrl.range)
 142
 143             if crossbar != None:
 144                 mem_ctrl.port = crossbar.master
 145             else:
 146                 mem_ctrl.port = dir_cntrl.memory
 147
 148             # Enable low-power DRAM states if option is set
 149             if issubclass(mem_type, DRAMCtrl):
 150                 mem_ctrl.enable_dram_powerdown = \
 151                         options.enable_dram_powerdown
 152
 153         index += 1
 154         dir_cntrl.addr_ranges = dir_ranges
 155
 156     system.mem_ctrls = mem_ctrls
 157
 158     if len(crossbars) > 0:
 159         ruby.crossbars = crossbars
 160
 161
 162 def create_topology(controllers, options):
 163     """ Called from create_system in configs/ruby/<protocol>.py
 164         Must return an object which is a subclass of BaseTopology
 165         found in configs/topologies/BaseTopology.py
 166         This is a wrapper for the legacy topologies.
 167     """
 168     exec("import topologies.%s as Topo" % options.topology)
 169     topology = eval("Topo.%s(controllers)" % options.topology)
 170     return topology
 171
 172 def create_system(options, full_system, system, piobus = None, dma_ports = [],
 173                   bootmem=None):
 174
 175     system.ruby = RubySystem()
 176     ruby = system.ruby
 177
 178     # Generate pseudo filesystem
 179     FileSystemConfig.config_filesystem(system, options)
 180
 181     # Create the network object
 182     (network, IntLinkClass, ExtLinkClass, RouterClass, InterfaceClass) = \
 183         Network.create_network(options, ruby)
 184     ruby.network = network
 185
 186     protocol = buildEnv['PROTOCOL']
 187     exec("from . import %s" % protocol)
 188     try:
 189         (cpu_sequencers, dir_cntrls, topology) = \
 190              eval("%s.create_system(options, full_system, system, dma_ports,\
 191                                     bootmem, ruby)"
 192                   % protocol)
 193     except:
 194         print("Error: could not create sytem for ruby protocol %s" % protocol)
 195         raise
 196
 197     # Create the network topology
 198     topology.makeTopology(options, network, IntLinkClass, ExtLinkClass,
 199             RouterClass)
 200
 201     # Register the topology elements with faux filesystem (SE mode only)
 202     if not full_system:
 203         topology.registerTopology(options)
 204
 205
 206     # Initialize network based on topology
 207     Network.init_network(options, network, InterfaceClass)
 208
 209     # Create a port proxy for connecting the system port. This is
 210     # independent of the protocol and kept in the protocol-agnostic
 211     # part (i.e. here).
 212     sys_port_proxy = RubyPortProxy(ruby_system = ruby)
 213     if piobus is not None:
 214         sys_port_proxy.pio_master_port = piobus.slave
 215
 216     # Give the system port proxy a SimObject parent without creating a
 217     # full-fledged controller
 218     system.sys_port_proxy = sys_port_proxy
 219
 220     # Connect the system port for loading of binaries etc
 221     system.system_port = system.sys_port_proxy.slave
 222
 223     setup_memory_controllers(system, ruby, dir_cntrls, options)
 224
 225     # Connect the cpu sequencers and the piobus
 226     if piobus != None:
 227         for cpu_seq in cpu_sequencers:
 228             cpu_seq.pio_master_port = piobus.slave
 229             cpu_seq.mem_master_port = piobus.slave
 230
 231             if buildEnv['TARGET_ISA'] == "x86":
 232                 cpu_seq.pio_slave_port = piobus.master
 233
 234     ruby.number_of_virtual_networks = ruby.network.number_of_virtual_networks
 235     ruby._cpu_ports = cpu_sequencers
 236     ruby.num_of_sequencers = len(cpu_sequencers)
 237
 238     # Create a backing copy of physical memory in case required
 239     if options.access_backing_store:
 240         ruby.access_backing_store = True
 241         ruby.phys_mem = SimpleMemory(range=system.mem_ranges[0],
 242                                      in_addr_map=False)
 243
 244 def create_directories(options, bootmem, ruby_system, system):
 245     dir_cntrl_nodes = []
 246     for i in range(options.num_dirs):
 247         dir_cntrl = Directory_Controller()
 248         dir_cntrl.version = i
 249         dir_cntrl.directory = RubyDirectoryMemory()
 250         dir_cntrl.ruby_system = ruby_system
 251
 252         exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
 253         dir_cntrl_nodes.append(dir_cntrl)
 254
 255     if bootmem is not None:
 256         rom_dir_cntrl = Directory_Controller()
 257         rom_dir_cntrl.directory = RubyDirectoryMemory()
 258         rom_dir_cntrl.ruby_system = ruby_system
 259         rom_dir_cntrl.version = i + 1
 260         rom_dir_cntrl.memory = bootmem.port
 261         rom_dir_cntrl.addr_ranges = bootmem.range
 262         return (dir_cntrl_nodes, rom_dir_cntrl)
 263
 264     return (dir_cntrl_nodes, None)
 265
 266 def send_evicts(options):
 267     # currently, 2 scenarios warrant forwarding evictions to the CPU:
 268     # 1. The O3 model must keep the LSQ coherent with the caches
 269     # 2. The x86 mwait instruction is built on top of coherence invalidations
 270     # 3. The local exclusive monitor in ARM systems
 271     if options.cpu_type == "DerivO3CPU" or \
 272        buildEnv['TARGET_ISA'] in ('x86', 'arm'):
 273         return True
 274     return False