1 # Copyright (c) 2012 ARM Limited
4 # The license below extends only to copyright in the software and shall
5 # not be construed as granting a license to any other intellectual
6 # property including but not limited to intellectual property relating
7 # to a hardware implementation of the functionality of the software
8 # licensed hereunder. You may use the software subject to the license
9 # terms below provided that you ensure that this notice is replicated
10 # unmodified and in its entirety in all distributions of the software,
11 # modified or unmodified, in source code or in binary form.
13 # Copyright (c) 2006-2007 The Regents of The University of Michigan
14 # Copyright (c) 2009 Advanced Micro Devices, Inc.
15 # All rights reserved.
17 # Redistribution and use in source and binary forms, with or without
18 # modification, are permitted provided that the following conditions are
19 # met: redistributions of source code must retain the above copyright
20 # notice, this list of conditions and the following disclaimer;
21 # redistributions in binary form must reproduce the above copyright
22 # notice, this list of conditions and the following disclaimer in the
23 # documentation and/or other materials provided with the distribution;
24 # neither the name of the copyright holders nor the names of its
25 # contributors may be used to endorse or promote products derived from
26 # this software without specific prior written permission.
28 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 # Authors: Brad Beckmann
44 from m5
.objects
import *
45 from m5
.defines
import buildEnv
46 from m5
.util
import addToPath
, fatal
48 addToPath('../topologies')
50 def define_options(parser
):
51 # By default, ruby uses the simple timing cpu
52 parser
.set_defaults(cpu_type
="timing")
54 parser
.add_option("--ruby-clock", action
="store", type="string",
56 help="Clock for blocks running at Ruby system's speed")
58 # Options related to cache structure
59 parser
.add_option("--ports", action
="store", type="int", default
=4,
60 help="used of transitions per cycle which is a proxy \
61 for the number of ports.")
63 # ruby network options
64 parser
.add_option("--topology", type="string", default
="Crossbar",
65 help="check src/mem/ruby/network/topologies for complete set")
66 parser
.add_option("--mesh-rows", type="int", default
=1,
67 help="the number of rows in the mesh topology")
68 parser
.add_option("--garnet-network", type="choice",
69 choices
=['fixed', 'flexible'], help="'fixed'|'flexible'")
70 parser
.add_option("--network-fault-model", action
="store_true", default
=False,
71 help="enable network fault model: see src/mem/ruby/network/fault_model/")
73 # ruby mapping options
74 parser
.add_option("--numa-high-bit", type="int", default
=0,
75 help="high order address bit to use for numa mapping. " \
76 "0 = highest bit, not specified = lowest bit")
78 # ruby sparse memory options
79 parser
.add_option("--use-map", action
="store_true", default
=False)
80 parser
.add_option("--map-levels", type="int", default
=4)
82 parser
.add_option("--recycle-latency", type="int", default
=10,
83 help="Recycle latency for ruby controller input buffers")
85 parser
.add_option("--random_seed", type="int", default
=1234,
86 help="Used for seeding the random number generator")
88 parser
.add_option("--ruby_stats", type="string", default
="ruby.stats")
90 protocol
= buildEnv
['PROTOCOL']
91 exec "import %s" % protocol
92 eval("%s.define_options(parser)" % protocol
)
94 def create_topology(controllers
, options
):
95 """ Called from create_system in configs/ruby/<protocol>.py
96 Must return an object which is a subclass of BaseTopology
97 found in configs/topologies/BaseTopology.py
98 This is a wrapper for the legacy topologies.
100 exec "import %s as Topo" % options
.topology
101 topology
= eval("Topo.%s(controllers)" % options
.topology
)
104 def create_system(options
, full_system
, system
, piobus
= None, dma_ports
= []):
106 system
.ruby
= RubySystem(no_mem_vec
= options
.use_map
)
109 # Set the network classes based on the command line options
110 if options
.garnet_network
== "fixed":
111 NetworkClass
= GarnetNetwork_d
112 IntLinkClass
= GarnetIntLink_d
113 ExtLinkClass
= GarnetExtLink_d
114 RouterClass
= GarnetRouter_d
115 InterfaceClass
= GarnetNetworkInterface_d
117 elif options
.garnet_network
== "flexible":
118 NetworkClass
= GarnetNetwork
119 IntLinkClass
= GarnetIntLink
120 ExtLinkClass
= GarnetExtLink
121 RouterClass
= GarnetRouter
122 InterfaceClass
= GarnetNetworkInterface
125 NetworkClass
= SimpleNetwork
126 IntLinkClass
= SimpleIntLink
127 ExtLinkClass
= SimpleExtLink
129 InterfaceClass
= None
131 # Instantiate the network object so that the controllers can connect to it.
132 network
= NetworkClass(ruby_system
= ruby
, topology
= options
.topology
,
133 routers
= [], ext_links
= [], int_links
= [], netifs
= [])
134 ruby
.network
= network
136 protocol
= buildEnv
['PROTOCOL']
137 exec "import %s" % protocol
139 (cpu_sequencers
, dir_cntrls
, topology
) = \
140 eval("%s.create_system(options, full_system, system, dma_ports,\
144 print "Error: could not create sytem for ruby protocol %s" % protocol
147 # Create a port proxy for connecting the system port. This is
148 # independent of the protocol and kept in the protocol-agnostic
150 sys_port_proxy
= RubyPortProxy(ruby_system
= ruby
)
152 # Give the system port proxy a SimObject parent without creating a
153 # full-fledged controller
154 system
.sys_port_proxy
= sys_port_proxy
156 # Connect the system port for loading of binaries etc
157 system
.system_port
= system
.sys_port_proxy
.slave
159 # Create the network topology
160 topology
.makeTopology(options
, network
, IntLinkClass
, ExtLinkClass
,
163 if InterfaceClass
!= None:
164 netifs
= [InterfaceClass(id=i
) for (i
,n
) in enumerate(network
.ext_links
)]
165 network
.netifs
= netifs
167 if options
.network_fault_model
:
168 assert(options
.garnet_network
== "fixed")
169 network
.enable_fault_model
= True
170 network
.fault_model
= FaultModel()
172 # Loop through the directory controlers.
173 # Determine the total memory size of the ruby system and verify it is equal
174 # to physmem. However, if Ruby memory is using sparse memory in SE
175 # mode, then the system should not back-up the memory state with
176 # the Memory Vector and thus the memory size bytes should stay at 0.
177 # Also set the numa bits to the appropriate values.
178 total_mem_size
= MemorySize('0B')
180 ruby
.block_size_bytes
= options
.cacheline_size
181 block_size_bits
= int(math
.log(options
.cacheline_size
, 2))
183 if options
.numa_high_bit
:
184 numa_bit
= options
.numa_high_bit
186 # if the numa_bit is not specified, set the directory bits as the
187 # lowest bits above the block offset bits, and the numa_bit as the
188 # highest of those directory bits
189 dir_bits
= int(math
.log(options
.num_dirs
, 2))
190 numa_bit
= block_size_bits
+ dir_bits
- 1
192 for dir_cntrl
in dir_cntrls
:
193 total_mem_size
.value
+= dir_cntrl
.directory
.size
.value
194 dir_cntrl
.directory
.numa_high_bit
= numa_bit
196 phys_mem_size
= sum(map(lambda r
: r
.size(), system
.mem_ranges
))
197 assert(total_mem_size
.value
== phys_mem_size
)
198 ruby
.mem_size
= total_mem_size
200 # Connect the cpu sequencers and the piobus
202 for cpu_seq
in cpu_sequencers
:
203 cpu_seq
.pio_master_port
= piobus
.slave
204 cpu_seq
.mem_master_port
= piobus
.slave
206 if buildEnv
['TARGET_ISA'] == "x86":
207 cpu_seq
.pio_slave_port
= piobus
.master
209 ruby
._cpu
_ports
= cpu_sequencers
210 ruby
.num_of_sequencers
= len(cpu_sequencers
)
211 ruby
.random_seed
= options
.random_seed