1 # Copyright (c) 2010 Advanced Micro Devices, Inc.
4 # Redistribution and use in source and binary forms, with or without
5 # modification, are permitted provided that the following conditions are
6 # met: redistributions of source code must retain the above copyright
7 # notice, this list of conditions and the following disclaimer;
8 # redistributions in binary form must reproduce the above copyright
9 # notice, this list of conditions and the following disclaimer in the
10 # documentation and/or other materials provided with the distribution;
11 # neither the name of the copyright holders nor the names of its
12 # contributors may be used to endorse or promote products derived from
13 # this software without specific prior written permission.
15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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25 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 from __future__
import print_function
28 from __future__
import absolute_import
30 from m5
.params
import *
31 from m5
.objects
import *
33 from common
import FileSystemConfig
35 from .BaseTopology
import SimpleTopology
37 # Creates a Mesh topology with 4 directories, one at each corner.
38 # One L1 (and L2, depending on the protocol) are connected to each router.
39 # XY routing is enforced (using link weights) to guarantee deadlock freedom.
41 class MeshDirCorners_XY(SimpleTopology
):
42 description
='MeshDirCorners_XY'
44 def __init__(self
, controllers
):
45 self
.nodes
= controllers
47 def makeTopology(self
, options
, network
, IntLink
, ExtLink
, Router
):
50 num_routers
= options
.num_cpus
51 num_rows
= options
.mesh_rows
53 # default values for link latency and router latency.
54 # Can be over-ridden on a per link/router basis
55 link_latency
= options
.link_latency
# used by simple and garnet
56 router_latency
= options
.router_latency
# only used by garnet
59 # First determine which nodes are cache cntrls vs. dirs vs. dma
64 if node
.type == 'L1Cache_Controller' or \
65 node
.type == 'L2Cache_Controller':
66 cache_nodes
.append(node
)
67 elif node
.type == 'Directory_Controller':
68 dir_nodes
.append(node
)
69 elif node
.type == 'DMA_Controller':
70 dma_nodes
.append(node
)
72 # Obviously the number or rows must be <= the number of routers
73 # and evenly divisible. Also the number of caches must be a
74 # multiple of the number of routers and the number of directories
76 assert(num_rows
> 0 and num_rows
<= num_routers
)
77 num_columns
= int(num_routers
/ num_rows
)
78 assert(num_columns
* num_rows
== num_routers
)
79 caches_per_router
, remainder
= divmod(len(cache_nodes
), num_routers
)
80 assert(remainder
== 0)
81 assert(len(dir_nodes
) == 4)
83 # Create the routers in the mesh
84 routers
= [Router(router_id
=i
, latency
= router_latency
) \
85 for i
in range(num_routers
)]
86 network
.routers
= routers
88 # link counter to set unique link ids
91 # Connect each cache controller to the appropriate router
93 for (i
, n
) in enumerate(cache_nodes
):
94 cntrl_level
, router_id
= divmod(i
, num_routers
)
95 assert(cntrl_level
< caches_per_router
)
96 ext_links
.append(ExtLink(link_id
=link_count
, ext_node
=n
,
97 int_node
=routers
[router_id
],
98 latency
= link_latency
))
101 # NUMA Node for each quadrant
102 # With odd columns or rows, the nodes will be unequal
103 numa_nodes
= [ [], [], [], []]
104 for i
in xrange(num_routers
):
105 if i
% num_columns
< num_columns
/ 2 and \
107 numa_nodes
[0].append(i
)
108 elif i
% num_columns
>= num_columns
/ 2 and \
110 numa_nodes
[1].append(i
)
111 elif i
% num_columns
< num_columns
/ 2 and \
112 i
>= num_routers
/ 2:
113 numa_nodes
[2].append(i
)
115 numa_nodes
[3].append(i
)
122 # Connect the dir nodes to the corners.
123 ext_links
.append(ExtLink(link_id
=link_count
, ext_node
=dir_nodes
[0],
125 latency
= link_latency
))
127 ext_links
.append(ExtLink(link_id
=link_count
, ext_node
=dir_nodes
[1],
128 int_node
=routers
[num_columns
- 1],
129 latency
= link_latency
))
131 ext_links
.append(ExtLink(link_id
=link_count
, ext_node
=dir_nodes
[2],
132 int_node
=routers
[num_routers
- num_columns
],
133 latency
= link_latency
))
135 ext_links
.append(ExtLink(link_id
=link_count
, ext_node
=dir_nodes
[3],
136 int_node
=routers
[num_routers
- 1],
137 latency
= link_latency
))
140 # Connect the dma nodes to router 0. These should only be DMA nodes.
141 for (i
, node
) in enumerate(dma_nodes
):
142 assert(node
.type == 'DMA_Controller')
143 ext_links
.append(ExtLink(link_id
=link_count
, ext_node
=node
,
145 latency
= link_latency
))
147 network
.ext_links
= ext_links
149 # Create the mesh links.
152 # East output to West input links (weight = 1)
153 for row
in range(num_rows
):
154 for col
in range(num_columns
):
155 if (col
+ 1 < num_columns
):
156 east_out
= col
+ (row
* num_columns
)
157 west_in
= (col
+ 1) + (row
* num_columns
)
158 int_links
.append(IntLink(link_id
=link_count
,
159 src_node
=routers
[east_out
],
160 dst_node
=routers
[west_in
],
163 latency
= link_latency
,
167 # West output to East input links (weight = 1)
168 for row
in range(num_rows
):
169 for col
in range(num_columns
):
170 if (col
+ 1 < num_columns
):
171 east_in
= col
+ (row
* num_columns
)
172 west_out
= (col
+ 1) + (row
* num_columns
)
173 int_links
.append(IntLink(link_id
=link_count
,
174 src_node
=routers
[west_out
],
175 dst_node
=routers
[east_in
],
178 latency
= link_latency
,
182 # North output to South input links (weight = 2)
183 for col
in range(num_columns
):
184 for row
in range(num_rows
):
185 if (row
+ 1 < num_rows
):
186 north_out
= col
+ (row
* num_columns
)
187 south_in
= col
+ ((row
+ 1) * num_columns
)
188 int_links
.append(IntLink(link_id
=link_count
,
189 src_node
=routers
[north_out
],
190 dst_node
=routers
[south_in
],
193 latency
= link_latency
,
197 # South output to North input links (weight = 2)
198 for col
in range(num_columns
):
199 for row
in range(num_rows
):
200 if (row
+ 1 < num_rows
):
201 north_in
= col
+ (row
* num_columns
)
202 south_out
= col
+ ((row
+ 1) * num_columns
)
203 int_links
.append(IntLink(link_id
=link_count
,
204 src_node
=routers
[south_out
],
205 dst_node
=routers
[north_in
],
208 latency
= link_latency
,
213 network
.int_links
= int_links
215 # Register nodes with filesystem
216 def registerTopology(self
, options
):
220 FileSystemConfig
.register_node(n
,
221 MemorySize(options
.mem_size
) / num_numa_nodes
, i
)