core.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7 use work.wishbone_types.all;
   8
   9 entity core is
  10     generic (
  11         SIM : boolean := false;
  12         DISABLE_FLATTEN : boolean := false
  13         );
  14     port (
  15         clk          : in std_logic;
  16         rst          : in std_logic;
  17
  18         wishbone_insn_in  : in wishbone_slave_out;
  19         wishbone_insn_out : out wishbone_master_out;
  20
  21         wishbone_data_in  : in wishbone_slave_out;
  22         wishbone_data_out : out wishbone_master_out;
  23
  24         dmi_addr        : in std_ulogic_vector(3 downto 0);
  25         dmi_din         : in std_ulogic_vector(63 downto 0);
  26         dmi_dout        : out std_ulogic_vector(63 downto 0);
  27         dmi_req         : in std_ulogic;
  28         dmi_wr          : in std_ulogic;
  29         dmi_ack         : out std_ulogic;
  30
  31         terminated_out   : out std_logic
  32         );
  33 end core;
  34
  35 architecture behave of core is
  36     -- fetch signals
  37     signal fetch2_to_decode1: Fetch2ToDecode1Type;
  38
  39     -- icache signals
  40     signal fetch1_to_icache : Fetch1ToIcacheType;
  41     signal icache_to_fetch2 : IcacheToFetch2Type;
  42
  43     -- decode signals
  44     signal decode1_to_decode2: Decode1ToDecode2Type;
  45     signal decode2_to_execute1: Decode2ToExecute1Type;
  46
  47     -- register file signals
  48     signal register_file_to_decode2: RegisterFileToDecode2Type;
  49     signal decode2_to_register_file: Decode2ToRegisterFileType;
  50     signal writeback_to_register_file: WritebackToRegisterFileType;
  51
  52     -- CR file signals
  53     signal decode2_to_cr_file: Decode2ToCrFileType;
  54     signal cr_file_to_decode2: CrFileToDecode2Type;
  55     signal writeback_to_cr_file: WritebackToCrFileType;
  56
  57     -- execute signals
  58     signal execute1_to_writeback: Execute1ToWritebackType;
  59     signal execute1_to_fetch1: Execute1ToFetch1Type;
  60
  61     -- load store signals
  62     signal decode2_to_loadstore1: Decode2ToLoadstore1Type;
  63     signal loadstore1_to_dcache: Loadstore1ToDcacheType;
  64     signal dcache_to_writeback: DcacheToWritebackType;
  65
  66     -- multiply signals
  67     signal decode2_to_multiply: Decode2ToMultiplyType;
  68     signal multiply_to_writeback: MultiplyToWritebackType;
  69
  70     -- divider signals
  71     signal decode2_to_divider: Decode2ToDividerType;
  72     signal divider_to_writeback: DividerToWritebackType;
  73
  74     -- local signals
  75     signal fetch1_stall_in : std_ulogic;
  76     signal icache_stall_out : std_ulogic;
  77     signal fetch2_stall_in : std_ulogic;
  78     signal decode1_stall_in : std_ulogic;
  79     signal decode2_stall_out : std_ulogic;
  80     signal ex1_icache_inval: std_ulogic;
  81
  82     signal flush: std_ulogic;
  83
  84     signal complete: std_ulogic;
  85     signal terminate: std_ulogic;
  86     signal core_rst: std_ulogic;
  87     signal icache_rst: std_ulogic;
  88
  89     -- Debug actions
  90     signal dbg_core_stop: std_ulogic;
  91     signal dbg_core_rst: std_ulogic;
  92     signal dbg_icache_rst: std_ulogic;
  93
  94     -- Debug status
  95     signal dbg_core_is_stopped: std_ulogic;
  96
  97     function keep_h(disable : boolean) return string is
  98     begin
  99         if disable then
 100             return "yes";
 101         else
 102             return "no";
 103         end if;
 104     end function;
 105     attribute keep_hierarchy : string;
 106     attribute keep_hierarchy of fetch1_0 : label is keep_h(DISABLE_FLATTEN);
 107     attribute keep_hierarchy of icache_0 : label is keep_h(DISABLE_FLATTEN);
 108     attribute keep_hierarchy of fetch2_0 : label is keep_h(DISABLE_FLATTEN);
 109     attribute keep_hierarchy of decode1_0 : label is keep_h(DISABLE_FLATTEN);
 110     attribute keep_hierarchy of decode2_0 : label is keep_h(DISABLE_FLATTEN);
 111     attribute keep_hierarchy of register_file_0 : label is keep_h(DISABLE_FLATTEN);
 112     attribute keep_hierarchy of cr_file_0 : label is keep_h(DISABLE_FLATTEN);
 113     attribute keep_hierarchy of execute1_0 : label is keep_h(DISABLE_FLATTEN);
 114     attribute keep_hierarchy of multiply_0 : label is keep_h(DISABLE_FLATTEN);
 115     attribute keep_hierarchy of divider_0 : label is keep_h(DISABLE_FLATTEN);
 116     attribute keep_hierarchy of loadstore1_0 : label is keep_h(DISABLE_FLATTEN);
 117     attribute keep_hierarchy of dcache_0 : label is keep_h(DISABLE_FLATTEN);
 118     attribute keep_hierarchy of writeback_0 : label is keep_h(DISABLE_FLATTEN);
 119     attribute keep_hierarchy of debug_0 : label is keep_h(DISABLE_FLATTEN);
 120 begin
 121
 122     core_rst <= dbg_core_rst or rst;
 123
 124     fetch1_0: entity work.fetch1
 125         generic map (
 126             RESET_ADDRESS => (others => '0')
 127             )
 128         port map (
 129             clk => clk,
 130             rst => core_rst,
 131             stall_in => fetch1_stall_in,
 132             flush_in => flush,
 133             stop_in => dbg_core_stop,
 134             e_in => execute1_to_fetch1,
 135             i_out => fetch1_to_icache
 136             );
 137
 138     fetch1_stall_in <= icache_stall_out or decode2_stall_out;
 139
 140     icache_0: entity work.icache
 141         generic map(
 142             LINE_SIZE => 64,
 143             NUM_LINES => 32,
 144             NUM_WAYS => 2
 145             )
 146         port map(
 147             clk => clk,
 148             rst => icache_rst,
 149             i_in => fetch1_to_icache,
 150             i_out => icache_to_fetch2,
 151             flush_in => flush,
 152             stall_out => icache_stall_out,
 153             wishbone_out => wishbone_insn_out,
 154             wishbone_in => wishbone_insn_in
 155             );
 156
 157     icache_rst <= rst or dbg_icache_rst or ex1_icache_inval;
 158
 159     fetch2_0: entity work.fetch2
 160         port map (
 161             clk => clk,
 162             rst => core_rst,
 163             stall_in => fetch2_stall_in,
 164             flush_in => flush,
 165             i_in => icache_to_fetch2,
 166             f_out => fetch2_to_decode1
 167             );
 168
 169     fetch2_stall_in <= decode2_stall_out;
 170
 171     decode1_0: entity work.decode1
 172         port map (
 173             clk => clk,
 174             rst => core_rst,
 175             stall_in => decode1_stall_in,
 176             flush_in => flush,
 177             f_in => fetch2_to_decode1,
 178             d_out => decode1_to_decode2
 179             );
 180
 181     decode1_stall_in <= decode2_stall_out;
 182
 183     decode2_0: entity work.decode2
 184         port map (
 185             clk => clk,
 186             rst => core_rst,
 187             stall_out => decode2_stall_out,
 188             flush_in => flush,
 189             complete_in => complete,
 190             stopped_out => dbg_core_is_stopped,
 191             d_in => decode1_to_decode2,
 192             e_out => decode2_to_execute1,
 193             l_out => decode2_to_loadstore1,
 194             m_out => decode2_to_multiply,
 195             d_out => decode2_to_divider,
 196             r_in => register_file_to_decode2,
 197             r_out => decode2_to_register_file,
 198             c_in => cr_file_to_decode2,
 199             c_out => decode2_to_cr_file
 200             );
 201
 202     register_file_0: entity work.register_file
 203         generic map (
 204             SIM => SIM
 205             )
 206         port map (
 207             clk => clk,
 208             d_in => decode2_to_register_file,
 209             d_out => register_file_to_decode2,
 210             w_in => writeback_to_register_file,
 211             sim_dump => terminate
 212             );
 213
 214     cr_file_0: entity work.cr_file
 215         port map (
 216             clk => clk,
 217             d_in => decode2_to_cr_file,
 218             d_out => cr_file_to_decode2,
 219             w_in => writeback_to_cr_file
 220             );
 221
 222     execute1_0: entity work.execute1
 223         port map (
 224             clk => clk,
 225             flush_out => flush,
 226             e_in => decode2_to_execute1,
 227             f_out => execute1_to_fetch1,
 228             e_out => execute1_to_writeback,
 229             icache_inval => ex1_icache_inval,
 230             terminate_out => terminate
 231             );
 232
 233     loadstore1_0: entity work.loadstore1
 234         port map (
 235             clk => clk,
 236             l_in => decode2_to_loadstore1,
 237             l_out => loadstore1_to_dcache
 238             );
 239
 240     dcache_0: entity work.dcache
 241         generic map(
 242             LINE_SIZE => 64,
 243             NUM_LINES => 32,
 244             NUM_WAYS => 2
 245             )
 246         port map (
 247             clk => clk,
 248             rst => core_rst,
 249             d_in => loadstore1_to_dcache,
 250             d_out => dcache_to_writeback,
 251             wishbone_in => wishbone_data_in,
 252             wishbone_out => wishbone_data_out
 253             );
 254
 255     multiply_0: entity work.multiply
 256         port map (
 257             clk => clk,
 258             m_in => decode2_to_multiply,
 259             m_out => multiply_to_writeback
 260             );
 261
 262     divider_0: entity work.divider
 263         port map (
 264             clk => clk,
 265             rst => core_rst,
 266             d_in => decode2_to_divider,
 267             d_out => divider_to_writeback
 268             );
 269
 270     writeback_0: entity work.writeback
 271         port map (
 272             clk => clk,
 273             e_in => execute1_to_writeback,
 274             l_in => dcache_to_writeback,
 275             m_in => multiply_to_writeback,
 276             d_in => divider_to_writeback,
 277             w_out => writeback_to_register_file,
 278             c_out => writeback_to_cr_file,
 279             complete_out => complete
 280             );
 281
 282     debug_0: entity work.core_debug
 283         port map (
 284             clk => clk,
 285             rst => rst,
 286             dmi_addr => dmi_addr,
 287             dmi_din => dmi_din,
 288             dmi_dout => dmi_dout,
 289             dmi_req => dmi_req,
 290             dmi_wr => dmi_wr,
 291             dmi_ack => dmi_ack,
 292             core_stop => dbg_core_stop,
 293             core_rst => dbg_core_rst,
 294             icache_rst => dbg_icache_rst,
 295             terminate => terminate,
 296             core_stopped => dbg_core_is_stopped,
 297             nia => fetch1_to_icache.nia,
 298             terminated_out => terminated_out
 299             );
 300
 301 end behave;