core.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7 use work.wishbone_types.all;
   8
   9 entity core is
  10     generic (
  11         SIM : boolean := false;
  12         DISABLE_FLATTEN : boolean := false;
  13         EX1_BYPASS : boolean := true;
  14         ALT_RESET_ADDRESS : std_ulogic_vector(63 downto 0) := (others => '0')
  15         );
  16     port (
  17         clk          : in std_ulogic;
  18         rst          : in std_ulogic;
  19
  20         -- Alternate reset (0xffff0000) for use by DRAM init fw
  21         alt_reset    : in std_ulogic;
  22
  23         -- Wishbone interface
  24         wishbone_insn_in  : in wishbone_slave_out;
  25         wishbone_insn_out : out wishbone_master_out;
  26
  27         wishbone_data_in  : in wishbone_slave_out;
  28         wishbone_data_out : out wishbone_master_out;
  29
  30         dmi_addr        : in std_ulogic_vector(3 downto 0);
  31         dmi_din         : in std_ulogic_vector(63 downto 0);
  32         dmi_dout        : out std_ulogic_vector(63 downto 0);
  33         dmi_req         : in std_ulogic;
  34         dmi_wr          : in std_ulogic;
  35         dmi_ack         : out std_ulogic;
  36
  37         ext_irq         : in std_ulogic;
  38
  39         terminated_out   : out std_logic
  40         );
  41 end core;
  42
  43 architecture behave of core is
  44     -- icache signals
  45     signal fetch1_to_icache : Fetch1ToIcacheType;
  46     signal icache_to_decode1 : IcacheToDecode1Type;
  47     signal mmu_to_icache : MmuToIcacheType;
  48
  49     -- decode signals
  50     signal decode1_to_decode2: Decode1ToDecode2Type;
  51     signal decode2_to_execute1: Decode2ToExecute1Type;
  52
  53     -- register file signals
  54     signal register_file_to_decode2: RegisterFileToDecode2Type;
  55     signal decode2_to_register_file: Decode2ToRegisterFileType;
  56     signal writeback_to_register_file: WritebackToRegisterFileType;
  57
  58     -- CR file signals
  59     signal decode2_to_cr_file: Decode2ToCrFileType;
  60     signal cr_file_to_decode2: CrFileToDecode2Type;
  61     signal writeback_to_cr_file: WritebackToCrFileType;
  62
  63     -- execute signals
  64     signal execute1_to_writeback: Execute1ToWritebackType;
  65     signal execute1_to_fetch1: Execute1ToFetch1Type;
  66
  67     -- load store signals
  68     signal execute1_to_loadstore1: Execute1ToLoadstore1Type;
  69     signal loadstore1_to_execute1: Loadstore1ToExecute1Type;
  70     signal loadstore1_to_writeback: Loadstore1ToWritebackType;
  71     signal loadstore1_to_mmu: Loadstore1ToMmuType;
  72     signal mmu_to_loadstore1: MmuToLoadstore1Type;
  73
  74     -- dcache signals
  75     signal loadstore1_to_dcache: Loadstore1ToDcacheType;
  76     signal dcache_to_loadstore1: DcacheToLoadstore1Type;
  77     signal mmu_to_dcache: MmuToDcacheType;
  78     signal dcache_to_mmu: DcacheToMmuType;
  79
  80     -- local signals
  81     signal fetch1_stall_in : std_ulogic;
  82     signal icache_stall_out : std_ulogic;
  83     signal icache_stall_in : std_ulogic;
  84     signal decode1_stall_in : std_ulogic;
  85     signal decode2_stall_in : std_ulogic;
  86     signal decode2_stall_out : std_ulogic;
  87     signal ex1_icache_inval: std_ulogic;
  88     signal ex1_stall_out: std_ulogic;
  89     signal ls1_stall_out: std_ulogic;
  90     signal dcache_stall_out: std_ulogic;
  91
  92     signal flush: std_ulogic;
  93
  94     signal complete: std_ulogic;
  95     signal terminate: std_ulogic;
  96     signal core_rst: std_ulogic;
  97     signal icache_inv: std_ulogic;
  98
  99     -- Delayed/Latched resets and alt_reset
 100     signal rst_fetch1  : std_ulogic := '1';
 101     signal rst_fetch2  : std_ulogic := '1';
 102     signal rst_icache  : std_ulogic := '1';
 103     signal rst_dcache  : std_ulogic := '1';
 104     signal rst_dec1    : std_ulogic := '1';
 105     signal rst_dec2    : std_ulogic := '1';
 106     signal rst_ex1     : std_ulogic := '1';
 107     signal rst_ls1     : std_ulogic := '1';
 108     signal rst_dbg     : std_ulogic := '1';
 109     signal alt_reset_d : std_ulogic;
 110
 111     signal sim_cr_dump: std_ulogic;
 112
 113     -- Debug actions
 114     signal dbg_core_stop: std_ulogic;
 115     signal dbg_core_rst: std_ulogic;
 116     signal dbg_icache_rst: std_ulogic;
 117
 118     signal dbg_gpr_req : std_ulogic;
 119     signal dbg_gpr_ack : std_ulogic;
 120     signal dbg_gpr_addr : gspr_index_t;
 121     signal dbg_gpr_data : std_ulogic_vector(63 downto 0);
 122
 123     signal msr : std_ulogic_vector(63 downto 0);
 124
 125     -- Debug status
 126     signal dbg_core_is_stopped: std_ulogic;
 127
 128     -- Logging signals
 129     signal log_data    : std_ulogic_vector(255 downto 0);
 130     signal log_rd_addr : std_ulogic_vector(31 downto 0);
 131     signal log_wr_addr : std_ulogic_vector(31 downto 0);
 132     signal log_rd_data : std_ulogic_vector(63 downto 0);
 133
 134     function keep_h(disable : boolean) return string is
 135     begin
 136         if disable then
 137             return "yes";
 138         else
 139             return "no";
 140         end if;
 141     end function;
 142     attribute keep_hierarchy : string;
 143     attribute keep_hierarchy of fetch1_0 : label is keep_h(DISABLE_FLATTEN);
 144     attribute keep_hierarchy of icache_0 : label is keep_h(DISABLE_FLATTEN);
 145     attribute keep_hierarchy of decode1_0 : label is keep_h(DISABLE_FLATTEN);
 146     attribute keep_hierarchy of decode2_0 : label is keep_h(DISABLE_FLATTEN);
 147     attribute keep_hierarchy of register_file_0 : label is keep_h(DISABLE_FLATTEN);
 148     attribute keep_hierarchy of cr_file_0 : label is keep_h(DISABLE_FLATTEN);
 149     attribute keep_hierarchy of execute1_0 : label is keep_h(DISABLE_FLATTEN);
 150     attribute keep_hierarchy of loadstore1_0 : label is keep_h(DISABLE_FLATTEN);
 151     attribute keep_hierarchy of mmu_0 : label is keep_h(DISABLE_FLATTEN);
 152     attribute keep_hierarchy of dcache_0 : label is keep_h(DISABLE_FLATTEN);
 153     attribute keep_hierarchy of writeback_0 : label is keep_h(DISABLE_FLATTEN);
 154     attribute keep_hierarchy of debug_0 : label is keep_h(DISABLE_FLATTEN);
 155 begin
 156
 157     core_rst <= dbg_core_rst or rst;
 158
 159     resets: process(clk)
 160     begin
 161         if rising_edge(clk) then
 162             rst_fetch1  <= core_rst;
 163             rst_fetch2  <= core_rst;
 164             rst_icache  <= core_rst;
 165             rst_dcache  <= core_rst;
 166             rst_dec1    <= core_rst;
 167             rst_dec2    <= core_rst;
 168             rst_ex1     <= core_rst;
 169             rst_ls1     <= core_rst;
 170             rst_dbg     <= rst;
 171             alt_reset_d <= alt_reset;
 172         end if;
 173     end process;
 174
 175     fetch1_0: entity work.fetch1
 176         generic map (
 177             RESET_ADDRESS => (others => '0'),
 178             ALT_RESET_ADDRESS => ALT_RESET_ADDRESS
 179             )
 180         port map (
 181             clk => clk,
 182             rst => rst_fetch1,
 183             alt_reset_in => alt_reset_d,
 184             stall_in => fetch1_stall_in,
 185             flush_in => flush,
 186             stop_in => dbg_core_stop,
 187             e_in => execute1_to_fetch1,
 188             i_out => fetch1_to_icache,
 189             log_out => log_data(42 downto 0)
 190             );
 191
 192     fetch1_stall_in <= icache_stall_out or decode2_stall_out;
 193
 194     icache_0: entity work.icache
 195         generic map(
 196             SIM => SIM,
 197             LINE_SIZE => 64,
 198             NUM_LINES => 64,
 199             NUM_WAYS => 2
 200             )
 201         port map(
 202             clk => clk,
 203             rst => rst_icache,
 204             i_in => fetch1_to_icache,
 205             i_out => icache_to_decode1,
 206             m_in => mmu_to_icache,
 207             flush_in => flush,
 208             inval_in => dbg_icache_rst or ex1_icache_inval,
 209             stall_in => icache_stall_in,
 210             stall_out => icache_stall_out,
 211             wishbone_out => wishbone_insn_out,
 212             wishbone_in => wishbone_insn_in,
 213             log_out => log_data(96 downto 43)
 214             );
 215
 216     icache_stall_in <= decode2_stall_out;
 217
 218     decode1_0: entity work.decode1
 219         port map (
 220             clk => clk,
 221             rst => rst_dec1,
 222             stall_in => decode1_stall_in,
 223             flush_in => flush,
 224             f_in => icache_to_decode1,
 225             d_out => decode1_to_decode2,
 226             log_out => log_data(109 downto 97)
 227             );
 228
 229     decode1_stall_in <= decode2_stall_out;
 230
 231     decode2_0: entity work.decode2
 232         generic map (
 233             EX1_BYPASS => EX1_BYPASS
 234             )
 235         port map (
 236             clk => clk,
 237             rst => rst_dec2,
 238             stall_in => decode2_stall_in,
 239             stall_out => decode2_stall_out,
 240             flush_in => flush,
 241             complete_in => complete,
 242             stopped_out => dbg_core_is_stopped,
 243             d_in => decode1_to_decode2,
 244             e_out => decode2_to_execute1,
 245             r_in => register_file_to_decode2,
 246             r_out => decode2_to_register_file,
 247             c_in => cr_file_to_decode2,
 248             c_out => decode2_to_cr_file,
 249             log_out => log_data(119 downto 110)
 250             );
 251     decode2_stall_in <= ex1_stall_out or ls1_stall_out;
 252
 253     register_file_0: entity work.register_file
 254         generic map (
 255             SIM => SIM
 256             )
 257         port map (
 258             clk => clk,
 259             d_in => decode2_to_register_file,
 260             d_out => register_file_to_decode2,
 261             w_in => writeback_to_register_file,
 262             dbg_gpr_req => dbg_gpr_req,
 263             dbg_gpr_ack => dbg_gpr_ack,
 264             dbg_gpr_addr => dbg_gpr_addr,
 265             dbg_gpr_data => dbg_gpr_data,
 266             sim_dump => terminate,
 267             sim_dump_done => sim_cr_dump,
 268             log_out => log_data(255 downto 185)
 269             );
 270
 271     cr_file_0: entity work.cr_file
 272         generic map (
 273             SIM => SIM
 274             )
 275         port map (
 276             clk => clk,
 277             d_in => decode2_to_cr_file,
 278             d_out => cr_file_to_decode2,
 279             w_in => writeback_to_cr_file,
 280             sim_dump => sim_cr_dump,
 281             log_out => log_data(184 downto 172)
 282             );
 283
 284     execute1_0: entity work.execute1
 285         generic map (
 286             EX1_BYPASS => EX1_BYPASS
 287             )
 288         port map (
 289             clk => clk,
 290             rst => rst_ex1,
 291             flush_out => flush,
 292             stall_out => ex1_stall_out,
 293             e_in => decode2_to_execute1,
 294             l_in => loadstore1_to_execute1,
 295             ext_irq_in => ext_irq,
 296             l_out => execute1_to_loadstore1,
 297             f_out => execute1_to_fetch1,
 298             e_out => execute1_to_writeback,
 299             icache_inval => ex1_icache_inval,
 300             dbg_msr_out => msr,
 301             terminate_out => terminate,
 302             log_out => log_data(134 downto 120),
 303             log_rd_addr => log_rd_addr,
 304             log_rd_data => log_rd_data,
 305             log_wr_addr => log_wr_addr
 306             );
 307
 308     loadstore1_0: entity work.loadstore1
 309         port map (
 310             clk => clk,
 311             rst => rst_ls1,
 312             l_in => execute1_to_loadstore1,
 313             e_out => loadstore1_to_execute1,
 314             l_out => loadstore1_to_writeback,
 315             d_out => loadstore1_to_dcache,
 316             d_in => dcache_to_loadstore1,
 317             m_out => loadstore1_to_mmu,
 318             m_in => mmu_to_loadstore1,
 319             dc_stall => dcache_stall_out,
 320             stall_out => ls1_stall_out,
 321             log_out => log_data(149 downto 140)
 322             );
 323
 324     mmu_0: entity work.mmu
 325         port map (
 326             clk => clk,
 327             rst => core_rst,
 328             l_in => loadstore1_to_mmu,
 329             l_out => mmu_to_loadstore1,
 330             d_out => mmu_to_dcache,
 331             d_in => dcache_to_mmu,
 332             i_out => mmu_to_icache
 333             );
 334
 335     dcache_0: entity work.dcache
 336         generic map(
 337             LINE_SIZE => 64,
 338             NUM_LINES => 64,
 339             NUM_WAYS => 2
 340             )
 341         port map (
 342             clk => clk,
 343             rst => rst_dcache,
 344             d_in => loadstore1_to_dcache,
 345             d_out => dcache_to_loadstore1,
 346             m_in => mmu_to_dcache,
 347             m_out => dcache_to_mmu,
 348             stall_out => dcache_stall_out,
 349             wishbone_in => wishbone_data_in,
 350             wishbone_out => wishbone_data_out,
 351             log_out => log_data(171 downto 152)
 352             );
 353
 354     writeback_0: entity work.writeback
 355         port map (
 356             clk => clk,
 357             e_in => execute1_to_writeback,
 358             l_in => loadstore1_to_writeback,
 359             w_out => writeback_to_register_file,
 360             c_out => writeback_to_cr_file,
 361             complete_out => complete
 362             );
 363
 364     log_data(151 downto 150) <= "00";
 365     log_data(139 downto 135) <= "00000";
 366
 367     debug_0: entity work.core_debug
 368         port map (
 369             clk => clk,
 370             rst => rst_dbg,
 371             dmi_addr => dmi_addr,
 372             dmi_din => dmi_din,
 373             dmi_dout => dmi_dout,
 374             dmi_req => dmi_req,
 375             dmi_wr => dmi_wr,
 376             dmi_ack => dmi_ack,
 377             core_stop => dbg_core_stop,
 378             core_rst => dbg_core_rst,
 379             icache_rst => dbg_icache_rst,
 380             terminate => terminate,
 381             core_stopped => dbg_core_is_stopped,
 382             nia => fetch1_to_icache.nia,
 383             msr => msr,
 384             dbg_gpr_req => dbg_gpr_req,
 385             dbg_gpr_ack => dbg_gpr_ack,
 386             dbg_gpr_addr => dbg_gpr_addr,
 387             dbg_gpr_data => dbg_gpr_data,
 388             log_data => log_data,
 389             log_read_addr => log_rd_addr,
 390             log_read_data => log_rd_data,
 391             log_write_addr => log_wr_addr,
 392             terminated_out => terminated_out
 393             );
 394
 395 end behave;