core.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7 use work.wishbone_types.all;
   8
   9 entity core is
  10     generic (
  11         SIM : boolean := false
  12         );
  13     port (
  14         clk          : in std_logic;
  15         rst          : in std_logic;
  16
  17         wishbone_insn_in  : in wishbone_slave_out;
  18         wishbone_insn_out : out wishbone_master_out;
  19
  20         wishbone_data_in  : in wishbone_slave_out;
  21         wishbone_data_out : out wishbone_master_out;
  22
  23         dmi_addr        : in std_ulogic_vector(3 downto 0);
  24         dmi_din         : in std_ulogic_vector(63 downto 0);
  25         dmi_dout        : out std_ulogic_vector(63 downto 0);
  26         dmi_req         : in std_ulogic;
  27         dmi_wr          : in std_ulogic;
  28         dmi_ack         : out std_ulogic;
  29
  30         terminated_out   : out std_logic
  31         );
  32 end core;
  33
  34 architecture behave of core is
  35     -- fetch signals
  36     signal fetch2_to_decode1: Fetch2ToDecode1Type;
  37
  38     -- icache signals
  39     signal fetch1_to_icache : Fetch1ToIcacheType;
  40     signal icache_to_fetch2 : IcacheToFetch2Type;
  41
  42     -- decode signals
  43     signal decode1_to_decode2: Decode1ToDecode2Type;
  44     signal decode2_to_execute1: Decode2ToExecute1Type;
  45
  46     -- register file signals
  47     signal register_file_to_decode2: RegisterFileToDecode2Type;
  48     signal decode2_to_register_file: Decode2ToRegisterFileType;
  49     signal writeback_to_register_file: WritebackToRegisterFileType;
  50
  51     -- CR file signals
  52     signal decode2_to_cr_file: Decode2ToCrFileType;
  53     signal cr_file_to_decode2: CrFileToDecode2Type;
  54     signal writeback_to_cr_file: WritebackToCrFileType;
  55
  56     -- execute signals
  57     signal execute1_to_execute2: Execute1ToExecute2Type;
  58     signal execute2_to_writeback: Execute2ToWritebackType;
  59     signal execute1_to_fetch1: Execute1ToFetch1Type;
  60
  61     -- load store signals
  62     signal decode2_to_loadstore1: Decode2ToLoadstore1Type;
  63     signal loadstore1_to_loadstore2: Loadstore1ToLoadstore2Type;
  64     signal loadstore2_to_writeback: Loadstore2ToWritebackType;
  65
  66     -- multiply signals
  67     signal decode2_to_multiply: Decode2ToMultiplyType;
  68     signal multiply_to_writeback: MultiplyToWritebackType;
  69
  70     -- divider signals
  71     signal decode2_to_divider: Decode2ToDividerType;
  72     signal divider_to_writeback: DividerToWritebackType;
  73
  74     -- local signals
  75     signal fetch1_stall_in : std_ulogic;
  76     signal icache_stall_out : std_ulogic;
  77     signal fetch2_stall_in : std_ulogic;
  78     signal decode1_stall_in : std_ulogic;
  79     signal decode2_stall_out : std_ulogic;
  80
  81     signal flush: std_ulogic;
  82
  83     signal complete: std_ulogic;
  84     signal terminate: std_ulogic;
  85     signal core_rst: std_ulogic;
  86     signal icache_rst: std_ulogic;
  87
  88     -- Debug actions
  89     signal dbg_core_stop: std_ulogic;
  90     signal dbg_core_rst: std_ulogic;
  91     signal dbg_icache_rst: std_ulogic;
  92
  93     -- Debug status
  94     signal dbg_core_is_stopped: std_ulogic;
  95
  96 begin
  97
  98     core_rst <= dbg_core_rst or rst;
  99
 100     fetch1_0: entity work.fetch1
 101         generic map (
 102             RESET_ADDRESS => (others => '0')
 103             )
 104         port map (
 105             clk => clk,
 106             rst => core_rst,
 107             stall_in => fetch1_stall_in,
 108             flush_in => flush,
 109             stop_in => dbg_core_stop,
 110             e_in => execute1_to_fetch1,
 111             i_out => fetch1_to_icache
 112             );
 113
 114     fetch1_stall_in <= icache_stall_out or decode2_stall_out;
 115
 116     icache_0: entity work.icache
 117         generic map(
 118             LINE_SIZE => 64,
 119             NUM_LINES => 16
 120             )
 121         port map(
 122             clk => clk,
 123             rst => icache_rst,
 124             i_in => fetch1_to_icache,
 125             i_out => icache_to_fetch2,
 126             flush_in => flush,
 127             stall_out => icache_stall_out,
 128             wishbone_out => wishbone_insn_out,
 129             wishbone_in => wishbone_insn_in
 130             );
 131
 132     icache_rst <= rst or dbg_icache_rst;
 133
 134     fetch2_0: entity work.fetch2
 135         port map (
 136             clk => clk,
 137             rst => core_rst,
 138             stall_in => fetch2_stall_in,
 139             flush_in => flush,
 140             i_in => icache_to_fetch2,
 141             f_out => fetch2_to_decode1
 142             );
 143
 144     fetch2_stall_in <= decode2_stall_out;
 145
 146     decode1_0: entity work.decode1
 147         port map (
 148             clk => clk,
 149             rst => core_rst,
 150             stall_in => decode1_stall_in,
 151             flush_in => flush,
 152             f_in => fetch2_to_decode1,
 153             d_out => decode1_to_decode2
 154             );
 155
 156     decode1_stall_in <= decode2_stall_out;
 157
 158     decode2_0: entity work.decode2
 159         port map (
 160             clk => clk,
 161             rst => core_rst,
 162             stall_out => decode2_stall_out,
 163             flush_in => flush,
 164             complete_in => complete,
 165             stopped_out => dbg_core_is_stopped,
 166             d_in => decode1_to_decode2,
 167             e_out => decode2_to_execute1,
 168             l_out => decode2_to_loadstore1,
 169             m_out => decode2_to_multiply,
 170             d_out => decode2_to_divider,
 171             r_in => register_file_to_decode2,
 172             r_out => decode2_to_register_file,
 173             c_in => cr_file_to_decode2,
 174             c_out => decode2_to_cr_file
 175             );
 176
 177     register_file_0: entity work.register_file
 178         generic map (
 179             SIM => SIM
 180             )
 181         port map (
 182             clk => clk,
 183             d_in => decode2_to_register_file,
 184             d_out => register_file_to_decode2,
 185             w_in => writeback_to_register_file,
 186             sim_dump => terminate
 187             );
 188
 189     cr_file_0: entity work.cr_file
 190         port map (
 191             clk => clk,
 192             d_in => decode2_to_cr_file,
 193             d_out => cr_file_to_decode2,
 194             w_in => writeback_to_cr_file
 195             );
 196
 197     execute1_0: entity work.execute1
 198         generic map (
 199             SIM => SIM
 200             )
 201         port map (
 202             clk => clk,
 203             flush_out => flush,
 204             e_in => decode2_to_execute1,
 205             f_out => execute1_to_fetch1,
 206             e_out => execute1_to_execute2,
 207             terminate_out => terminate
 208             );
 209
 210     execute2_0: entity work.execute2
 211         port map (
 212             clk => clk,
 213             e_in => execute1_to_execute2,
 214             e_out => execute2_to_writeback
 215             );
 216
 217     loadstore1_0: entity work.loadstore1
 218         port map (
 219             clk => clk,
 220             l_in => decode2_to_loadstore1,
 221             l_out => loadstore1_to_loadstore2
 222             );
 223
 224     loadstore2_0: entity work.loadstore2
 225         port map (
 226             clk => clk,
 227             l_in => loadstore1_to_loadstore2,
 228             w_out => loadstore2_to_writeback,
 229             m_in => wishbone_data_in,
 230             m_out => wishbone_data_out
 231             );
 232
 233     multiply_0: entity work.multiply
 234         port map (
 235             clk => clk,
 236             m_in => decode2_to_multiply,
 237             m_out => multiply_to_writeback
 238             );
 239
 240     divider_0: entity work.divider
 241         port map (
 242             clk => clk,
 243             rst => rst,
 244             d_in => decode2_to_divider,
 245             d_out => divider_to_writeback
 246             );
 247
 248     writeback_0: entity work.writeback
 249         port map (
 250             clk => clk,
 251             e_in => execute2_to_writeback,
 252             l_in => loadstore2_to_writeback,
 253             m_in => multiply_to_writeback,
 254             d_in => divider_to_writeback,
 255             w_out => writeback_to_register_file,
 256             c_out => writeback_to_cr_file,
 257             complete_out => complete
 258             );
 259
 260     debug_0: entity work.core_debug
 261         port map (
 262             clk => clk,
 263             rst => rst,
 264             dmi_addr => dmi_addr,
 265             dmi_din => dmi_din,
 266             dmi_dout => dmi_dout,
 267             dmi_req => dmi_req,
 268             dmi_wr => dmi_wr,
 269             dmi_ack => dmi_ack,
 270             core_stop => dbg_core_stop,
 271             core_rst => dbg_core_rst,
 272             icache_rst => dbg_icache_rst,
 273             terminate => terminate,
 274             core_stopped => dbg_core_is_stopped,
 275             nia => fetch1_to_icache.nia,
 276             terminated_out => terminated_out
 277             );
 278
 279 end behave;