core.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7 use work.wishbone_types.all;
   8
   9 entity core is
  10     generic (
  11         SIM : boolean := false;
  12         DISABLE_FLATTEN : boolean := false;
  13         EX1_BYPASS : boolean := true;
  14         HAS_FPU : boolean := true;
  15         HAS_BTC : boolean := true;
  16         HAS_SHORT_MULT : boolean := false;
  17         ALT_RESET_ADDRESS : std_ulogic_vector(63 downto 0) := (others => '0');
  18         LOG_LENGTH : natural := 512;
  19         ICACHE_NUM_LINES : natural := 64;
  20         ICACHE_NUM_WAYS : natural := 2;
  21         ICACHE_TLB_SIZE : natural := 64;
  22         DCACHE_NUM_LINES : natural := 64;
  23         DCACHE_NUM_WAYS : natural := 2;
  24         DCACHE_TLB_SET_SIZE : natural := 64;
  25         DCACHE_TLB_NUM_WAYS : natural := 2
  26         );
  27     port (
  28         clk          : in std_ulogic;
  29         rst          : in std_ulogic;
  30
  31         -- Alternate reset (0xffff0000) for use by DRAM init fw
  32         alt_reset    : in std_ulogic;
  33
  34         -- Wishbone interface
  35         wishbone_insn_in  : in wishbone_slave_out;
  36         wishbone_insn_out : out wishbone_master_out;
  37
  38         wishbone_data_in  : in wishbone_slave_out;
  39         wishbone_data_out : out wishbone_master_out;
  40
  41         wb_snoop_in     : in wishbone_master_out;
  42
  43         dmi_addr        : in std_ulogic_vector(3 downto 0);
  44         dmi_din         : in std_ulogic_vector(63 downto 0);
  45         dmi_dout        : out std_ulogic_vector(63 downto 0);
  46         dmi_req         : in std_ulogic;
  47         dmi_wr          : in std_ulogic;
  48         dmi_ack         : out std_ulogic;
  49
  50         ext_irq         : in std_ulogic;
  51
  52         terminated_out   : out std_logic
  53         );
  54 end core;
  55
  56 architecture behave of core is
  57     -- icache signals
  58     signal fetch1_to_icache : Fetch1ToIcacheType;
  59     signal writeback_to_fetch1: WritebackToFetch1Type;
  60     signal icache_to_decode1 : IcacheToDecode1Type;
  61     signal mmu_to_icache : MmuToIcacheType;
  62
  63     -- decode signals
  64     signal decode1_to_decode2: Decode1ToDecode2Type;
  65     signal decode1_to_fetch1: Decode1ToFetch1Type;
  66     signal decode2_to_execute1: Decode2ToExecute1Type;
  67
  68     -- register file signals
  69     signal register_file_to_decode2: RegisterFileToDecode2Type;
  70     signal decode2_to_register_file: Decode2ToRegisterFileType;
  71     signal writeback_to_register_file: WritebackToRegisterFileType;
  72
  73     -- CR file signals
  74     signal decode2_to_cr_file: Decode2ToCrFileType;
  75     signal cr_file_to_decode2: CrFileToDecode2Type;
  76     signal writeback_to_cr_file: WritebackToCrFileType;
  77
  78     -- execute signals
  79     signal execute1_to_writeback: Execute1ToWritebackType;
  80     signal execute1_bypass: bypass_data_t;
  81     signal execute1_cr_bypass: cr_bypass_data_t;
  82
  83     -- load store signals
  84     signal execute1_to_loadstore1: Execute1ToLoadstore1Type;
  85     signal loadstore1_to_execute1: Loadstore1ToExecute1Type;
  86     signal loadstore1_to_writeback: Loadstore1ToWritebackType;
  87     signal loadstore1_to_mmu: Loadstore1ToMmuType;
  88     signal mmu_to_loadstore1: MmuToLoadstore1Type;
  89
  90     -- dcache signals
  91     signal loadstore1_to_dcache: Loadstore1ToDcacheType;
  92     signal dcache_to_loadstore1: DcacheToLoadstore1Type;
  93     signal mmu_to_dcache: MmuToDcacheType;
  94     signal dcache_to_mmu: DcacheToMmuType;
  95
  96     -- FPU signals
  97     signal execute1_to_fpu: Execute1ToFPUType;
  98     signal fpu_to_execute1: FPUToExecute1Type;
  99     signal fpu_to_writeback: FPUToWritebackType;
 100
 101     -- local signals
 102     signal fetch1_stall_in : std_ulogic;
 103     signal icache_stall_out : std_ulogic;
 104     signal icache_stall_in : std_ulogic;
 105     signal decode1_stall_in : std_ulogic;
 106     signal decode1_busy     : std_ulogic;
 107     signal decode2_busy_in : std_ulogic;
 108     signal decode2_stall_out : std_ulogic;
 109     signal ex1_icache_inval: std_ulogic;
 110     signal ex1_busy_out: std_ulogic;
 111     signal dcache_stall_out: std_ulogic;
 112
 113     signal flush: std_ulogic;
 114     signal decode1_flush: std_ulogic;
 115     signal fetch1_flush: std_ulogic;
 116
 117     signal complete: instr_tag_t;
 118     signal terminate: std_ulogic;
 119     signal core_rst: std_ulogic;
 120     signal icache_inv: std_ulogic;
 121     signal do_interrupt: std_ulogic;
 122
 123     -- Delayed/Latched resets and alt_reset
 124     signal rst_fetch1  : std_ulogic := '1';
 125     signal rst_fetch2  : std_ulogic := '1';
 126     signal rst_icache  : std_ulogic := '1';
 127     signal rst_dcache  : std_ulogic := '1';
 128     signal rst_dec1    : std_ulogic := '1';
 129     signal rst_dec2    : std_ulogic := '1';
 130     signal rst_ex1     : std_ulogic := '1';
 131     signal rst_fpu     : std_ulogic := '1';
 132     signal rst_ls1     : std_ulogic := '1';
 133     signal rst_wback   : std_ulogic := '1';
 134     signal rst_dbg     : std_ulogic := '1';
 135     signal alt_reset_d : std_ulogic;
 136
 137     signal sim_cr_dump: std_ulogic;
 138
 139     -- Debug actions
 140     signal dbg_core_stop: std_ulogic;
 141     signal dbg_core_rst: std_ulogic;
 142     signal dbg_icache_rst: std_ulogic;
 143
 144     signal dbg_gpr_req : std_ulogic;
 145     signal dbg_gpr_ack : std_ulogic;
 146     signal dbg_gpr_addr : gspr_index_t;
 147     signal dbg_gpr_data : std_ulogic_vector(63 downto 0);
 148
 149     signal msr : std_ulogic_vector(63 downto 0);
 150
 151     -- PMU event bus
 152     signal icache_events    : IcacheEventType;
 153     signal loadstore_events : Loadstore1EventType;
 154     signal dcache_events    : DcacheEventType;
 155     signal writeback_events : WritebackEventType;
 156
 157     -- Debug status
 158     signal dbg_core_is_stopped: std_ulogic;
 159
 160     -- Logging signals
 161     signal log_data    : std_ulogic_vector(255 downto 0);
 162     signal log_rd_addr : std_ulogic_vector(31 downto 0);
 163     signal log_wr_addr : std_ulogic_vector(31 downto 0);
 164     signal log_rd_data : std_ulogic_vector(63 downto 0);
 165
 166     function keep_h(disable : boolean) return string is
 167     begin
 168         if disable then
 169             return "yes";
 170         else
 171             return "no";
 172         end if;
 173     end function;
 174     attribute keep_hierarchy : string;
 175     attribute keep_hierarchy of fetch1_0 : label is keep_h(DISABLE_FLATTEN);
 176     attribute keep_hierarchy of icache_0 : label is keep_h(DISABLE_FLATTEN);
 177     attribute keep_hierarchy of decode1_0 : label is keep_h(DISABLE_FLATTEN);
 178     attribute keep_hierarchy of decode2_0 : label is keep_h(DISABLE_FLATTEN);
 179     attribute keep_hierarchy of register_file_0 : label is keep_h(DISABLE_FLATTEN);
 180     attribute keep_hierarchy of cr_file_0 : label is keep_h(DISABLE_FLATTEN);
 181     attribute keep_hierarchy of execute1_0 : label is keep_h(DISABLE_FLATTEN);
 182     attribute keep_hierarchy of loadstore1_0 : label is keep_h(DISABLE_FLATTEN);
 183     attribute keep_hierarchy of mmu_0 : label is keep_h(DISABLE_FLATTEN);
 184     attribute keep_hierarchy of dcache_0 : label is keep_h(DISABLE_FLATTEN);
 185     attribute keep_hierarchy of writeback_0 : label is keep_h(DISABLE_FLATTEN);
 186     attribute keep_hierarchy of debug_0 : label is keep_h(DISABLE_FLATTEN);
 187 begin
 188
 189     core_rst <= dbg_core_rst or rst;
 190
 191     resets: process(clk)
 192     begin
 193         if rising_edge(clk) then
 194             rst_fetch1  <= core_rst;
 195             rst_fetch2  <= core_rst;
 196             rst_icache  <= core_rst;
 197             rst_dcache  <= core_rst;
 198             rst_dec1    <= core_rst;
 199             rst_dec2    <= core_rst;
 200             rst_ex1     <= core_rst;
 201             rst_fpu     <= core_rst;
 202             rst_ls1     <= core_rst;
 203             rst_wback   <= core_rst;
 204             rst_dbg     <= rst;
 205             alt_reset_d <= alt_reset;
 206         end if;
 207     end process;
 208
 209     fetch1_0: entity work.fetch1
 210         generic map (
 211             RESET_ADDRESS => (others => '0'),
 212             ALT_RESET_ADDRESS => ALT_RESET_ADDRESS,
 213             HAS_BTC => HAS_BTC
 214             )
 215         port map (
 216             clk => clk,
 217             rst => rst_fetch1,
 218             alt_reset_in => alt_reset_d,
 219             stall_in => fetch1_stall_in,
 220             flush_in => fetch1_flush,
 221             inval_btc => ex1_icache_inval or mmu_to_icache.tlbie,
 222             stop_in => dbg_core_stop,
 223             d_in => decode1_to_fetch1,
 224             w_in => writeback_to_fetch1,
 225             i_out => fetch1_to_icache,
 226             log_out => log_data(42 downto 0)
 227             );
 228
 229     fetch1_stall_in <= icache_stall_out or decode1_busy;
 230     fetch1_flush <= flush or decode1_flush;
 231
 232     icache_0: entity work.icache
 233         generic map(
 234             SIM => SIM,
 235             LINE_SIZE => 64,
 236             NUM_LINES => ICACHE_NUM_LINES,
 237             NUM_WAYS => ICACHE_NUM_WAYS,
 238             TLB_SIZE => ICACHE_TLB_SIZE,
 239             LOG_LENGTH => LOG_LENGTH
 240             )
 241         port map(
 242             clk => clk,
 243             rst => rst_icache,
 244             i_in => fetch1_to_icache,
 245             i_out => icache_to_decode1,
 246             m_in => mmu_to_icache,
 247             flush_in => fetch1_flush,
 248             inval_in => dbg_icache_rst or ex1_icache_inval,
 249             stall_in => icache_stall_in,
 250             stall_out => icache_stall_out,
 251             wishbone_out => wishbone_insn_out,
 252             wishbone_in => wishbone_insn_in,
 253             wb_snoop_in => wb_snoop_in,
 254             events => icache_events,
 255             log_out => log_data(96 downto 43)
 256             );
 257
 258     icache_stall_in <= decode1_busy;
 259
 260     decode1_0: entity work.decode1
 261         generic map(
 262             HAS_FPU => HAS_FPU,
 263             LOG_LENGTH => LOG_LENGTH
 264             )
 265         port map (
 266             clk => clk,
 267             rst => rst_dec1,
 268             stall_in => decode1_stall_in,
 269             flush_in => flush,
 270             flush_out => decode1_flush,
 271             busy_out => decode1_busy,
 272             f_in => icache_to_decode1,
 273             d_out => decode1_to_decode2,
 274             f_out => decode1_to_fetch1,
 275             log_out => log_data(109 downto 97)
 276             );
 277
 278     decode1_stall_in <= decode2_stall_out;
 279
 280     decode2_0: entity work.decode2
 281         generic map (
 282             EX1_BYPASS => EX1_BYPASS,
 283             HAS_FPU => HAS_FPU,
 284             LOG_LENGTH => LOG_LENGTH
 285             )
 286         port map (
 287             clk => clk,
 288             rst => rst_dec2,
 289             busy_in => decode2_busy_in,
 290             stall_out => decode2_stall_out,
 291             flush_in => flush,
 292             complete_in => complete,
 293             stopped_out => dbg_core_is_stopped,
 294             d_in => decode1_to_decode2,
 295             e_out => decode2_to_execute1,
 296             r_in => register_file_to_decode2,
 297             r_out => decode2_to_register_file,
 298             c_in => cr_file_to_decode2,
 299             c_out => decode2_to_cr_file,
 300             execute_bypass => execute1_bypass,
 301             execute_cr_bypass => execute1_cr_bypass,
 302             log_out => log_data(119 downto 110)
 303             );
 304     decode2_busy_in <= ex1_busy_out;
 305
 306     register_file_0: entity work.register_file
 307         generic map (
 308             SIM => SIM,
 309             HAS_FPU => HAS_FPU,
 310             LOG_LENGTH => LOG_LENGTH
 311             )
 312         port map (
 313             clk => clk,
 314             d_in => decode2_to_register_file,
 315             d_out => register_file_to_decode2,
 316             w_in => writeback_to_register_file,
 317             dbg_gpr_req => dbg_gpr_req,
 318             dbg_gpr_ack => dbg_gpr_ack,
 319             dbg_gpr_addr => dbg_gpr_addr,
 320             dbg_gpr_data => dbg_gpr_data,
 321             sim_dump => terminate,
 322             sim_dump_done => sim_cr_dump,
 323             log_out => log_data(255 downto 184)
 324             );
 325
 326     cr_file_0: entity work.cr_file
 327         generic map (
 328             SIM => SIM,
 329             LOG_LENGTH => LOG_LENGTH
 330             )
 331         port map (
 332             clk => clk,
 333             d_in => decode2_to_cr_file,
 334             d_out => cr_file_to_decode2,
 335             w_in => writeback_to_cr_file,
 336             sim_dump => sim_cr_dump,
 337             log_out => log_data(183 downto 171)
 338             );
 339
 340     execute1_0: entity work.execute1
 341         generic map (
 342             EX1_BYPASS => EX1_BYPASS,
 343             HAS_FPU => HAS_FPU,
 344             HAS_SHORT_MULT => HAS_SHORT_MULT,
 345             LOG_LENGTH => LOG_LENGTH
 346             )
 347         port map (
 348             clk => clk,
 349             rst => rst_ex1,
 350             flush_in => flush,
 351             busy_out => ex1_busy_out,
 352             e_in => decode2_to_execute1,
 353             l_in => loadstore1_to_execute1,
 354             fp_in => fpu_to_execute1,
 355             ext_irq_in => ext_irq,
 356             interrupt_in => do_interrupt,
 357             l_out => execute1_to_loadstore1,
 358             fp_out => execute1_to_fpu,
 359             e_out => execute1_to_writeback,
 360             bypass_data => execute1_bypass,
 361             bypass_cr_data => execute1_cr_bypass,
 362             icache_inval => ex1_icache_inval,
 363             dbg_msr_out => msr,
 364             wb_events => writeback_events,
 365             ls_events => loadstore_events,
 366             dc_events => dcache_events,
 367             ic_events => icache_events,
 368             terminate_out => terminate,
 369             log_out => log_data(134 downto 120),
 370             log_rd_addr => log_rd_addr,
 371             log_rd_data => log_rd_data,
 372             log_wr_addr => log_wr_addr
 373             );
 374
 375     with_fpu: if HAS_FPU generate
 376     begin
 377         fpu_0: entity work.fpu
 378             port map (
 379                 clk => clk,
 380                 rst => rst_fpu,
 381                 e_in => execute1_to_fpu,
 382                 e_out => fpu_to_execute1,
 383                 w_out => fpu_to_writeback
 384                 );
 385     end generate;
 386
 387     no_fpu: if not HAS_FPU generate
 388     begin
 389         fpu_to_execute1 <= FPUToExecute1Init;
 390         fpu_to_writeback <= FPUToWritebackInit;
 391     end generate;
 392
 393     loadstore1_0: entity work.loadstore1
 394         generic map (
 395             HAS_FPU => HAS_FPU,
 396             LOG_LENGTH => LOG_LENGTH
 397             )
 398         port map (
 399             clk => clk,
 400             rst => rst_ls1,
 401             l_in => execute1_to_loadstore1,
 402             e_out => loadstore1_to_execute1,
 403             l_out => loadstore1_to_writeback,
 404             d_out => loadstore1_to_dcache,
 405             d_in => dcache_to_loadstore1,
 406             m_out => loadstore1_to_mmu,
 407             m_in => mmu_to_loadstore1,
 408             dc_stall => dcache_stall_out,
 409             events => loadstore_events,
 410             log_out => log_data(149 downto 140)
 411             );
 412
 413     mmu_0: entity work.mmu
 414         port map (
 415             clk => clk,
 416             rst => core_rst,
 417             l_in => loadstore1_to_mmu,
 418             l_out => mmu_to_loadstore1,
 419             d_out => mmu_to_dcache,
 420             d_in => dcache_to_mmu,
 421             i_out => mmu_to_icache
 422             );
 423
 424     dcache_0: entity work.dcache
 425         generic map(
 426             LINE_SIZE => 64,
 427             NUM_LINES => DCACHE_NUM_LINES,
 428             NUM_WAYS => DCACHE_NUM_WAYS,
 429             TLB_SET_SIZE => DCACHE_TLB_SET_SIZE,
 430             TLB_NUM_WAYS => DCACHE_TLB_NUM_WAYS,
 431             LOG_LENGTH => LOG_LENGTH
 432             )
 433         port map (
 434             clk => clk,
 435             rst => rst_dcache,
 436             d_in => loadstore1_to_dcache,
 437             d_out => dcache_to_loadstore1,
 438             m_in => mmu_to_dcache,
 439             m_out => dcache_to_mmu,
 440             stall_out => dcache_stall_out,
 441             wishbone_in => wishbone_data_in,
 442             wishbone_out => wishbone_data_out,
 443             snoop_in => wb_snoop_in,
 444             events => dcache_events,
 445             log_out => log_data(170 downto 151)
 446             );
 447
 448     writeback_0: entity work.writeback
 449         port map (
 450             clk => clk,
 451             rst => rst_wback,
 452             flush_out => flush,
 453             e_in => execute1_to_writeback,
 454             l_in => loadstore1_to_writeback,
 455             fp_in => fpu_to_writeback,
 456             w_out => writeback_to_register_file,
 457             c_out => writeback_to_cr_file,
 458             f_out => writeback_to_fetch1,
 459             events => writeback_events,
 460             interrupt_out => do_interrupt,
 461             complete_out => complete
 462             );
 463
 464     log_data(150) <= '0';
 465     log_data(139 downto 135) <= "00000";
 466
 467     debug_0: entity work.core_debug
 468         generic map (
 469             LOG_LENGTH => LOG_LENGTH
 470             )
 471         port map (
 472             clk => clk,
 473             rst => rst_dbg,
 474             dmi_addr => dmi_addr,
 475             dmi_din => dmi_din,
 476             dmi_dout => dmi_dout,
 477             dmi_req => dmi_req,
 478             dmi_wr => dmi_wr,
 479             dmi_ack => dmi_ack,
 480             core_stop => dbg_core_stop,
 481             core_rst => dbg_core_rst,
 482             icache_rst => dbg_icache_rst,
 483             terminate => terminate,
 484             core_stopped => dbg_core_is_stopped,
 485             nia => fetch1_to_icache.nia,
 486             msr => msr,
 487             dbg_gpr_req => dbg_gpr_req,
 488             dbg_gpr_ack => dbg_gpr_ack,
 489             dbg_gpr_addr => dbg_gpr_addr,
 490             dbg_gpr_data => dbg_gpr_data,
 491             log_data => log_data,
 492             log_read_addr => log_rd_addr,
 493             log_read_data => log_rd_data,
 494             log_write_addr => log_wr_addr,
 495             terminated_out => terminated_out
 496             );
 497
 498 end behave;