core.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7 use work.wishbone_types.all;
   8
   9 entity core is
  10     generic (
  11         SIM : boolean := false;
  12         DISABLE_FLATTEN : boolean := false;
  13         EX1_BYPASS : boolean := true;
  14         ALT_RESET_ADDRESS : std_ulogic_vector(63 downto 0) := (others => '0')
  15         );
  16     port (
  17         clk          : in std_ulogic;
  18         rst          : in std_ulogic;
  19
  20         -- Alternate reset (0xffff0000) for use by DRAM init fw
  21         alt_reset    : in std_ulogic;
  22
  23         -- Wishbone interface
  24         wishbone_insn_in  : in wishbone_slave_out;
  25         wishbone_insn_out : out wishbone_master_out;
  26
  27         wishbone_data_in  : in wishbone_slave_out;
  28         wishbone_data_out : out wishbone_master_out;
  29
  30         dmi_addr        : in std_ulogic_vector(3 downto 0);
  31         dmi_din         : in std_ulogic_vector(63 downto 0);
  32         dmi_dout        : out std_ulogic_vector(63 downto 0);
  33         dmi_req         : in std_ulogic;
  34         dmi_wr          : in std_ulogic;
  35         dmi_ack         : out std_ulogic;
  36
  37         ext_irq         : in std_ulogic;
  38
  39         terminated_out   : out std_logic
  40         );
  41 end core;
  42
  43 architecture behave of core is
  44     -- fetch signals
  45     signal fetch2_to_decode1: Fetch2ToDecode1Type;
  46
  47     -- icache signals
  48     signal fetch1_to_icache : Fetch1ToIcacheType;
  49     signal icache_to_fetch2 : IcacheToFetch2Type;
  50     signal mmu_to_icache : MmuToIcacheType;
  51
  52     -- decode signals
  53     signal decode1_to_decode2: Decode1ToDecode2Type;
  54     signal decode2_to_execute1: Decode2ToExecute1Type;
  55
  56     -- register file signals
  57     signal register_file_to_decode2: RegisterFileToDecode2Type;
  58     signal decode2_to_register_file: Decode2ToRegisterFileType;
  59     signal writeback_to_register_file: WritebackToRegisterFileType;
  60
  61     -- CR file signals
  62     signal decode2_to_cr_file: Decode2ToCrFileType;
  63     signal cr_file_to_decode2: CrFileToDecode2Type;
  64     signal writeback_to_cr_file: WritebackToCrFileType;
  65
  66     -- execute signals
  67     signal execute1_to_writeback: Execute1ToWritebackType;
  68     signal execute1_to_fetch1: Execute1ToFetch1Type;
  69
  70     -- load store signals
  71     signal execute1_to_loadstore1: Execute1ToLoadstore1Type;
  72     signal loadstore1_to_execute1: Loadstore1ToExecute1Type;
  73     signal loadstore1_to_writeback: Loadstore1ToWritebackType;
  74     signal loadstore1_to_mmu: Loadstore1ToMmuType;
  75     signal mmu_to_loadstore1: MmuToLoadstore1Type;
  76
  77     -- dcache signals
  78     signal loadstore1_to_dcache: Loadstore1ToDcacheType;
  79     signal dcache_to_loadstore1: DcacheToLoadstore1Type;
  80     signal mmu_to_dcache: MmuToDcacheType;
  81     signal dcache_to_mmu: DcacheToMmuType;
  82
  83     -- local signals
  84     signal fetch1_stall_in : std_ulogic;
  85     signal icache_stall_out : std_ulogic;
  86     signal fetch2_stall_in : std_ulogic;
  87     signal decode1_stall_in : std_ulogic;
  88     signal decode2_stall_in : std_ulogic;
  89     signal decode2_stall_out : std_ulogic;
  90     signal ex1_icache_inval: std_ulogic;
  91     signal ex1_stall_out: std_ulogic;
  92     signal ls1_stall_out: std_ulogic;
  93     signal dcache_stall_out: std_ulogic;
  94
  95     signal flush: std_ulogic;
  96
  97     signal complete: std_ulogic;
  98     signal terminate: std_ulogic;
  99     signal core_rst: std_ulogic;
 100     signal icache_inv: std_ulogic;
 101
 102     -- Delayed/Latched resets and alt_reset
 103     signal rst_fetch1  : std_ulogic := '1';
 104     signal rst_fetch2  : std_ulogic := '1';
 105     signal rst_icache  : std_ulogic := '1';
 106     signal rst_dcache  : std_ulogic := '1';
 107     signal rst_dec1    : std_ulogic := '1';
 108     signal rst_dec2    : std_ulogic := '1';
 109     signal rst_ex1     : std_ulogic := '1';
 110     signal rst_ls1     : std_ulogic := '1';
 111     signal rst_dbg     : std_ulogic := '1';
 112     signal alt_reset_d : std_ulogic;
 113
 114     signal sim_cr_dump: std_ulogic;
 115
 116     -- Debug actions
 117     signal dbg_core_stop: std_ulogic;
 118     signal dbg_core_rst: std_ulogic;
 119     signal dbg_icache_rst: std_ulogic;
 120
 121     signal dbg_gpr_req : std_ulogic;
 122     signal dbg_gpr_ack : std_ulogic;
 123     signal dbg_gpr_addr : gspr_index_t;
 124     signal dbg_gpr_data : std_ulogic_vector(63 downto 0);
 125
 126     signal msr : std_ulogic_vector(63 downto 0);
 127
 128     -- Debug status
 129     signal dbg_core_is_stopped: std_ulogic;
 130
 131     function keep_h(disable : boolean) return string is
 132     begin
 133         if disable then
 134             return "yes";
 135         else
 136             return "no";
 137         end if;
 138     end function;
 139     attribute keep_hierarchy : string;
 140     attribute keep_hierarchy of fetch1_0 : label is keep_h(DISABLE_FLATTEN);
 141     attribute keep_hierarchy of icache_0 : label is keep_h(DISABLE_FLATTEN);
 142     attribute keep_hierarchy of fetch2_0 : label is keep_h(DISABLE_FLATTEN);
 143     attribute keep_hierarchy of decode1_0 : label is keep_h(DISABLE_FLATTEN);
 144     attribute keep_hierarchy of decode2_0 : label is keep_h(DISABLE_FLATTEN);
 145     attribute keep_hierarchy of register_file_0 : label is keep_h(DISABLE_FLATTEN);
 146     attribute keep_hierarchy of cr_file_0 : label is keep_h(DISABLE_FLATTEN);
 147     attribute keep_hierarchy of execute1_0 : label is keep_h(DISABLE_FLATTEN);
 148     attribute keep_hierarchy of loadstore1_0 : label is keep_h(DISABLE_FLATTEN);
 149     attribute keep_hierarchy of mmu_0 : label is keep_h(DISABLE_FLATTEN);
 150     attribute keep_hierarchy of dcache_0 : label is keep_h(DISABLE_FLATTEN);
 151     attribute keep_hierarchy of writeback_0 : label is keep_h(DISABLE_FLATTEN);
 152     attribute keep_hierarchy of debug_0 : label is keep_h(DISABLE_FLATTEN);
 153 begin
 154
 155     core_rst <= dbg_core_rst or rst;
 156
 157     resets: process(clk)
 158     begin
 159         if rising_edge(clk) then
 160             rst_fetch1  <= core_rst;
 161             rst_fetch2  <= core_rst;
 162             rst_icache  <= core_rst or dbg_icache_rst or ex1_icache_inval;
 163             rst_dcache  <= core_rst;
 164             rst_dec1    <= core_rst;
 165             rst_dec2    <= core_rst;
 166             rst_ex1     <= core_rst;
 167             rst_ls1     <= core_rst;
 168             rst_dbg     <= rst;
 169             alt_reset_d <= alt_reset;
 170         end if;
 171     end process;
 172
 173     fetch1_0: entity work.fetch1
 174         generic map (
 175             RESET_ADDRESS => (others => '0'),
 176             ALT_RESET_ADDRESS => ALT_RESET_ADDRESS
 177             )
 178         port map (
 179             clk => clk,
 180             rst => rst_fetch1,
 181             alt_reset_in => alt_reset_d,
 182             stall_in => fetch1_stall_in,
 183             flush_in => flush,
 184             stop_in => dbg_core_stop,
 185             e_in => execute1_to_fetch1,
 186             i_out => fetch1_to_icache
 187             );
 188
 189     fetch1_stall_in <= icache_stall_out or decode2_stall_out;
 190
 191     icache_0: entity work.icache
 192         generic map(
 193             SIM => SIM,
 194             LINE_SIZE => 64,
 195             NUM_LINES => 32,
 196             NUM_WAYS => 2
 197             )
 198         port map(
 199             clk => clk,
 200             rst => rst_icache,
 201             i_in => fetch1_to_icache,
 202             i_out => icache_to_fetch2,
 203             m_in => mmu_to_icache,
 204             flush_in => flush,
 205             stall_out => icache_stall_out,
 206             wishbone_out => wishbone_insn_out,
 207             wishbone_in => wishbone_insn_in
 208             );
 209
 210     fetch2_0: entity work.fetch2
 211         port map (
 212             clk => clk,
 213             rst => rst_fetch2,
 214             stall_in => fetch2_stall_in,
 215             flush_in => flush,
 216             i_in => icache_to_fetch2,
 217             f_out => fetch2_to_decode1
 218             );
 219
 220     fetch2_stall_in <= decode2_stall_out;
 221
 222     decode1_0: entity work.decode1
 223         port map (
 224             clk => clk,
 225             rst => rst_dec1,
 226             stall_in => decode1_stall_in,
 227             flush_in => flush,
 228             f_in => fetch2_to_decode1,
 229             d_out => decode1_to_decode2
 230             );
 231
 232     decode1_stall_in <= decode2_stall_out;
 233
 234     decode2_0: entity work.decode2
 235         generic map (
 236             EX1_BYPASS => EX1_BYPASS
 237             )
 238         port map (
 239             clk => clk,
 240             rst => rst_dec2,
 241             stall_in => decode2_stall_in,
 242             stall_out => decode2_stall_out,
 243             flush_in => flush,
 244             complete_in => complete,
 245             stopped_out => dbg_core_is_stopped,
 246             d_in => decode1_to_decode2,
 247             e_out => decode2_to_execute1,
 248             r_in => register_file_to_decode2,
 249             r_out => decode2_to_register_file,
 250             c_in => cr_file_to_decode2,
 251             c_out => decode2_to_cr_file
 252             );
 253     decode2_stall_in <= ex1_stall_out or ls1_stall_out;
 254
 255     register_file_0: entity work.register_file
 256         generic map (
 257             SIM => SIM
 258             )
 259         port map (
 260             clk => clk,
 261             d_in => decode2_to_register_file,
 262             d_out => register_file_to_decode2,
 263             w_in => writeback_to_register_file,
 264             dbg_gpr_req => dbg_gpr_req,
 265             dbg_gpr_ack => dbg_gpr_ack,
 266             dbg_gpr_addr => dbg_gpr_addr,
 267             dbg_gpr_data => dbg_gpr_data,
 268             sim_dump => terminate,
 269             sim_dump_done => sim_cr_dump
 270             );
 271
 272     cr_file_0: entity work.cr_file
 273         generic map (
 274             SIM => SIM
 275             )
 276         port map (
 277             clk => clk,
 278             d_in => decode2_to_cr_file,
 279             d_out => cr_file_to_decode2,
 280             w_in => writeback_to_cr_file,
 281             sim_dump => sim_cr_dump
 282             );
 283
 284     execute1_0: entity work.execute1
 285         generic map (
 286             EX1_BYPASS => EX1_BYPASS
 287             )
 288         port map (
 289             clk => clk,
 290             rst => rst_ex1,
 291             flush_out => flush,
 292             stall_out => ex1_stall_out,
 293             e_in => decode2_to_execute1,
 294             l_in => loadstore1_to_execute1,
 295             ext_irq_in => ext_irq,
 296             l_out => execute1_to_loadstore1,
 297             f_out => execute1_to_fetch1,
 298             e_out => execute1_to_writeback,
 299             icache_inval => ex1_icache_inval,
 300             dbg_msr_out => msr,
 301             terminate_out => terminate
 302             );
 303
 304     loadstore1_0: entity work.loadstore1
 305         port map (
 306             clk => clk,
 307             rst => rst_ls1,
 308             l_in => execute1_to_loadstore1,
 309             e_out => loadstore1_to_execute1,
 310             l_out => loadstore1_to_writeback,
 311             d_out => loadstore1_to_dcache,
 312             d_in => dcache_to_loadstore1,
 313             m_out => loadstore1_to_mmu,
 314             m_in => mmu_to_loadstore1,
 315             dc_stall => dcache_stall_out,
 316             stall_out => ls1_stall_out
 317             );
 318
 319     mmu_0: entity work.mmu
 320         port map (
 321             clk => clk,
 322             rst => core_rst,
 323             l_in => loadstore1_to_mmu,
 324             l_out => mmu_to_loadstore1,
 325             d_out => mmu_to_dcache,
 326             d_in => dcache_to_mmu,
 327             i_out => mmu_to_icache
 328             );
 329
 330     dcache_0: entity work.dcache
 331         generic map(
 332             LINE_SIZE => 64,
 333             NUM_LINES => 32,
 334             NUM_WAYS => 2
 335             )
 336         port map (
 337             clk => clk,
 338             rst => rst_dcache,
 339             d_in => loadstore1_to_dcache,
 340             d_out => dcache_to_loadstore1,
 341             m_in => mmu_to_dcache,
 342             m_out => dcache_to_mmu,
 343             stall_out => dcache_stall_out,
 344             wishbone_in => wishbone_data_in,
 345             wishbone_out => wishbone_data_out
 346             );
 347
 348     writeback_0: entity work.writeback
 349         port map (
 350             clk => clk,
 351             e_in => execute1_to_writeback,
 352             l_in => loadstore1_to_writeback,
 353             w_out => writeback_to_register_file,
 354             c_out => writeback_to_cr_file,
 355             complete_out => complete
 356             );
 357
 358     debug_0: entity work.core_debug
 359         port map (
 360             clk => clk,
 361             rst => rst_dbg,
 362             dmi_addr => dmi_addr,
 363             dmi_din => dmi_din,
 364             dmi_dout => dmi_dout,
 365             dmi_req => dmi_req,
 366             dmi_wr => dmi_wr,
 367             dmi_ack => dmi_ack,
 368             core_stop => dbg_core_stop,
 369             core_rst => dbg_core_rst,
 370             icache_rst => dbg_icache_rst,
 371             terminate => terminate,
 372             core_stopped => dbg_core_is_stopped,
 373             nia => fetch1_to_icache.nia,
 374             msr => msr,
 375             dbg_gpr_req => dbg_gpr_req,
 376             dbg_gpr_ack => dbg_gpr_ack,
 377             dbg_gpr_addr => dbg_gpr_addr,
 378             dbg_gpr_data => dbg_gpr_data,
 379             terminated_out => terminated_out
 380             );
 381
 382 end behave;