core.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7 use work.wishbone_types.all;
   8
   9 entity core is
  10     generic (
  11         SIM : boolean := false
  12         );
  13     port (
  14         clk          : in std_logic;
  15         rst          : in std_logic;
  16
  17         wishbone_insn_in  : in wishbone_slave_out;
  18         wishbone_insn_out : out wishbone_master_out;
  19
  20         wishbone_data_in  : in wishbone_slave_out;
  21         wishbone_data_out : out wishbone_master_out;
  22
  23         -- Added for debug, ghdl doesn't support external names unfortunately
  24         registers     : out regfile;
  25         terminate_out : out std_ulogic
  26         );
  27 end core;
  28
  29 architecture behave of core is
  30     -- fetch signals
  31     signal fetch1_to_fetch2: Fetch1ToFetch2Type;
  32     signal fetch2_to_decode1: Fetch2ToDecode1Type;
  33
  34     -- icache signals
  35     signal fetch2_to_icache : Fetch2ToIcacheType;
  36     signal icache_to_fetch2 : IcacheToFetch2Type;
  37
  38     -- decode signals
  39     signal decode1_to_decode2: Decode1ToDecode2Type;
  40     signal decode2_to_execute1: Decode2ToExecute1Type;
  41
  42     -- register file signals
  43     signal register_file_to_decode2: RegisterFileToDecode2Type;
  44     signal decode2_to_register_file: Decode2ToRegisterFileType;
  45     signal writeback_to_register_file: WritebackToRegisterFileType;
  46
  47     -- CR file signals
  48     signal decode2_to_cr_file: Decode2ToCrFileType;
  49     signal cr_file_to_decode2: CrFileToDecode2Type;
  50     signal writeback_to_cr_file: WritebackToCrFileType;
  51
  52     -- execute signals
  53     signal execute1_to_execute2: Execute1ToExecute2Type;
  54     signal execute2_to_writeback: Execute2ToWritebackType;
  55     signal execute1_to_fetch1: Execute1ToFetch1Type;
  56
  57     -- load store signals
  58     signal decode2_to_loadstore1: Decode2ToLoadstore1Type;
  59     signal loadstore1_to_loadstore2: Loadstore1ToLoadstore2Type;
  60     signal loadstore2_to_writeback: Loadstore2ToWritebackType;
  61
  62     -- multiply signals
  63     signal decode2_to_multiply: Decode2ToMultiplyType;
  64     signal multiply_to_writeback: MultiplyToWritebackType;
  65
  66     -- local signals
  67     signal fetch1_stall_in : std_ulogic;
  68     signal fetch2_stall_in : std_ulogic;
  69     signal fetch2_stall_out : std_ulogic;
  70     signal decode1_stall_in : std_ulogic;
  71     signal decode2_stall_out : std_ulogic;
  72
  73     signal flush: std_ulogic;
  74
  75     signal complete: std_ulogic;
  76
  77     signal terminate: std_ulogic;
  78 begin
  79
  80     terminate_out <= terminate;
  81
  82     fetch1_0: entity work.fetch1
  83         generic map (
  84             RESET_ADDRESS => (others => '0')
  85             )
  86         port map (
  87             clk => clk,
  88             rst => rst,
  89             stall_in => fetch1_stall_in,
  90             flush_in => flush,
  91             e_in => execute1_to_fetch1,
  92             f_out => fetch1_to_fetch2
  93             );
  94
  95     fetch1_stall_in <= fetch2_stall_out or decode2_stall_out;
  96
  97     fetch2_0: entity work.fetch2
  98         port map (
  99             clk => clk,
 100             rst => rst,
 101             stall_in => fetch2_stall_in,
 102             stall_out => fetch2_stall_out,
 103             flush_in => flush,
 104             i_in => icache_to_fetch2,
 105             i_out => fetch2_to_icache,
 106             f_in => fetch1_to_fetch2,
 107             f_out => fetch2_to_decode1
 108             );
 109
 110     fetch2_stall_in <= decode2_stall_out;
 111
 112     icache_0: entity work.icache
 113         generic map(
 114             LINE_SIZE_DW => 8,
 115             NUM_LINES => 16
 116             )
 117         port map(
 118             clk => clk,
 119             rst => rst,
 120             i_in => fetch2_to_icache,
 121             i_out => icache_to_fetch2,
 122             wishbone_out => wishbone_insn_out,
 123             wishbone_in => wishbone_insn_in
 124             );
 125
 126     decode1_0: entity work.decode1
 127         port map (
 128             clk => clk,
 129             rst => rst,
 130             stall_in => decode1_stall_in,
 131             flush_in => flush,
 132             f_in => fetch2_to_decode1,
 133             d_out => decode1_to_decode2
 134             );
 135
 136     decode1_stall_in <= decode2_stall_out;
 137
 138     decode2_0: entity work.decode2
 139         port map (
 140             clk => clk,
 141             rst => rst,
 142             stall_out => decode2_stall_out,
 143             flush_in => flush,
 144             complete_in => complete,
 145             d_in => decode1_to_decode2,
 146             e_out => decode2_to_execute1,
 147             l_out => decode2_to_loadstore1,
 148             m_out => decode2_to_multiply,
 149             r_in => register_file_to_decode2,
 150             r_out => decode2_to_register_file,
 151             c_in => cr_file_to_decode2,
 152             c_out => decode2_to_cr_file
 153             );
 154
 155     register_file_0: entity work.register_file
 156         port map (
 157             clk => clk,
 158             d_in => decode2_to_register_file,
 159             d_out => register_file_to_decode2,
 160             w_in => writeback_to_register_file,
 161             registers_out => registers);
 162
 163     cr_file_0: entity work.cr_file
 164         port map (
 165             clk => clk,
 166             d_in => decode2_to_cr_file,
 167             d_out => cr_file_to_decode2,
 168             w_in => writeback_to_cr_file
 169             );
 170
 171     execute1_0: entity work.execute1
 172         generic map (
 173             SIM => SIM
 174             )
 175         port map (
 176             clk => clk,
 177             flush_out => flush,
 178             e_in => decode2_to_execute1,
 179             f_out => execute1_to_fetch1,
 180             e_out => execute1_to_execute2,
 181             terminate_out => terminate
 182             );
 183
 184     execute2_0: entity work.execute2
 185         port map (
 186             clk => clk,
 187             e_in => execute1_to_execute2,
 188             e_out => execute2_to_writeback
 189             );
 190
 191     loadstore1_0: entity work.loadstore1
 192         port map (
 193             clk => clk,
 194             l_in => decode2_to_loadstore1,
 195             l_out => loadstore1_to_loadstore2
 196             );
 197
 198     loadstore2_0: entity work.loadstore2
 199         port map (
 200             clk => clk,
 201             l_in => loadstore1_to_loadstore2,
 202             w_out => loadstore2_to_writeback,
 203             m_in => wishbone_data_in,
 204             m_out => wishbone_data_out
 205             );
 206
 207     multiply_0: entity work.multiply
 208         port map (
 209             clk => clk,
 210             m_in => decode2_to_multiply,
 211             m_out => multiply_to_writeback
 212             );
 213
 214     writeback_0: entity work.writeback
 215         port map (
 216             clk => clk,
 217             e_in => execute2_to_writeback,
 218             l_in => loadstore2_to_writeback,
 219             m_in => multiply_to_writeback,
 220             w_out => writeback_to_register_file,
 221             c_out => writeback_to_cr_file,
 222             complete_out => complete
 223             );
 224
 225 end behave;