core.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7 use work.wishbone_types.all;
   8
   9 entity core is
  10     generic (
  11         SIM : boolean := false;
  12         DISABLE_FLATTEN : boolean := false;
  13         EX1_BYPASS : boolean := true
  14         );
  15     port (
  16         clk          : in std_logic;
  17         rst          : in std_logic;
  18
  19         wishbone_insn_in  : in wishbone_slave_out;
  20         wishbone_insn_out : out wishbone_master_out;
  21
  22         wishbone_data_in  : in wishbone_slave_out;
  23         wishbone_data_out : out wishbone_master_out;
  24
  25         dmi_addr        : in std_ulogic_vector(3 downto 0);
  26         dmi_din         : in std_ulogic_vector(63 downto 0);
  27         dmi_dout        : out std_ulogic_vector(63 downto 0);
  28         dmi_req         : in std_ulogic;
  29         dmi_wr          : in std_ulogic;
  30         dmi_ack         : out std_ulogic;
  31
  32         terminated_out   : out std_logic
  33         );
  34 end core;
  35
  36 architecture behave of core is
  37     -- fetch signals
  38     signal fetch2_to_decode1: Fetch2ToDecode1Type;
  39
  40     -- icache signals
  41     signal fetch1_to_icache : Fetch1ToIcacheType;
  42     signal icache_to_fetch2 : IcacheToFetch2Type;
  43
  44     -- decode signals
  45     signal decode1_to_decode2: Decode1ToDecode2Type;
  46     signal decode2_to_execute1: Decode2ToExecute1Type;
  47
  48     -- register file signals
  49     signal register_file_to_decode2: RegisterFileToDecode2Type;
  50     signal decode2_to_register_file: Decode2ToRegisterFileType;
  51     signal writeback_to_register_file: WritebackToRegisterFileType;
  52
  53     -- CR file signals
  54     signal decode2_to_cr_file: Decode2ToCrFileType;
  55     signal cr_file_to_decode2: CrFileToDecode2Type;
  56     signal writeback_to_cr_file: WritebackToCrFileType;
  57
  58     -- execute signals
  59     signal execute1_to_writeback: Execute1ToWritebackType;
  60     signal execute1_to_fetch1: Execute1ToFetch1Type;
  61
  62     -- load store signals
  63     signal execute1_to_loadstore1: Execute1ToLoadstore1Type;
  64     signal loadstore1_to_writeback: Loadstore1ToWritebackType;
  65
  66     -- dcache signals
  67     signal loadstore1_to_dcache: Loadstore1ToDcacheType;
  68     signal dcache_to_loadstore1: DcacheToLoadstore1Type;
  69
  70     -- local signals
  71     signal fetch1_stall_in : std_ulogic;
  72     signal icache_stall_out : std_ulogic;
  73     signal fetch2_stall_in : std_ulogic;
  74     signal decode1_stall_in : std_ulogic;
  75     signal decode2_stall_in : std_ulogic;
  76     signal decode2_stall_out : std_ulogic;
  77     signal ex1_icache_inval: std_ulogic;
  78     signal ex1_stall_out: std_ulogic;
  79     signal ls1_stall_out: std_ulogic;
  80     signal dcache_stall_out: std_ulogic;
  81
  82     signal flush: std_ulogic;
  83
  84     signal complete: std_ulogic;
  85     signal terminate: std_ulogic;
  86     signal core_rst: std_ulogic;
  87     signal icache_rst: std_ulogic;
  88
  89     signal sim_cr_dump: std_ulogic;
  90
  91     -- Debug actions
  92     signal dbg_core_stop: std_ulogic;
  93     signal dbg_core_rst: std_ulogic;
  94     signal dbg_icache_rst: std_ulogic;
  95
  96     -- Debug status
  97     signal dbg_core_is_stopped: std_ulogic;
  98
  99     function keep_h(disable : boolean) return string is
 100     begin
 101         if disable then
 102             return "yes";
 103         else
 104             return "no";
 105         end if;
 106     end function;
 107     attribute keep_hierarchy : string;
 108     attribute keep_hierarchy of fetch1_0 : label is keep_h(DISABLE_FLATTEN);
 109     attribute keep_hierarchy of icache_0 : label is keep_h(DISABLE_FLATTEN);
 110     attribute keep_hierarchy of fetch2_0 : label is keep_h(DISABLE_FLATTEN);
 111     attribute keep_hierarchy of decode1_0 : label is keep_h(DISABLE_FLATTEN);
 112     attribute keep_hierarchy of decode2_0 : label is keep_h(DISABLE_FLATTEN);
 113     attribute keep_hierarchy of register_file_0 : label is keep_h(DISABLE_FLATTEN);
 114     attribute keep_hierarchy of cr_file_0 : label is keep_h(DISABLE_FLATTEN);
 115     attribute keep_hierarchy of execute1_0 : label is keep_h(DISABLE_FLATTEN);
 116     attribute keep_hierarchy of loadstore1_0 : label is keep_h(DISABLE_FLATTEN);
 117     attribute keep_hierarchy of dcache_0 : label is keep_h(DISABLE_FLATTEN);
 118     attribute keep_hierarchy of writeback_0 : label is keep_h(DISABLE_FLATTEN);
 119     attribute keep_hierarchy of debug_0 : label is keep_h(DISABLE_FLATTEN);
 120 begin
 121
 122     core_rst <= dbg_core_rst or rst;
 123
 124     fetch1_0: entity work.fetch1
 125         generic map (
 126             RESET_ADDRESS => (others => '0')
 127             )
 128         port map (
 129             clk => clk,
 130             rst => core_rst,
 131             stall_in => fetch1_stall_in,
 132             flush_in => flush,
 133             stop_in => dbg_core_stop,
 134             e_in => execute1_to_fetch1,
 135             i_out => fetch1_to_icache
 136             );
 137
 138     fetch1_stall_in <= icache_stall_out or decode2_stall_out;
 139
 140     icache_0: entity work.icache
 141         generic map(
 142             SIM => SIM,
 143             LINE_SIZE => 64,
 144             NUM_LINES => 32,
 145             NUM_WAYS => 2
 146             )
 147         port map(
 148             clk => clk,
 149             rst => icache_rst,
 150             i_in => fetch1_to_icache,
 151             i_out => icache_to_fetch2,
 152             flush_in => flush,
 153             stall_out => icache_stall_out,
 154             wishbone_out => wishbone_insn_out,
 155             wishbone_in => wishbone_insn_in
 156             );
 157
 158     icache_rst <= rst or dbg_icache_rst or ex1_icache_inval;
 159
 160     fetch2_0: entity work.fetch2
 161         port map (
 162             clk => clk,
 163             rst => core_rst,
 164             stall_in => fetch2_stall_in,
 165             flush_in => flush,
 166             i_in => icache_to_fetch2,
 167             f_out => fetch2_to_decode1
 168             );
 169
 170     fetch2_stall_in <= decode2_stall_out;
 171
 172     decode1_0: entity work.decode1
 173         port map (
 174             clk => clk,
 175             rst => core_rst,
 176             stall_in => decode1_stall_in,
 177             flush_in => flush,
 178             f_in => fetch2_to_decode1,
 179             d_out => decode1_to_decode2
 180             );
 181
 182     decode1_stall_in <= decode2_stall_out;
 183
 184     decode2_0: entity work.decode2
 185         generic map (
 186             EX1_BYPASS => EX1_BYPASS
 187             )
 188         port map (
 189             clk => clk,
 190             rst => core_rst,
 191             stall_in => decode2_stall_in,
 192             stall_out => decode2_stall_out,
 193             flush_in => flush,
 194             complete_in => complete,
 195             stopped_out => dbg_core_is_stopped,
 196             d_in => decode1_to_decode2,
 197             e_out => decode2_to_execute1,
 198             r_in => register_file_to_decode2,
 199             r_out => decode2_to_register_file,
 200             c_in => cr_file_to_decode2,
 201             c_out => decode2_to_cr_file
 202             );
 203     decode2_stall_in <= ex1_stall_out or ls1_stall_out;
 204
 205     register_file_0: entity work.register_file
 206         generic map (
 207             SIM => SIM
 208             )
 209         port map (
 210             clk => clk,
 211             d_in => decode2_to_register_file,
 212             d_out => register_file_to_decode2,
 213             w_in => writeback_to_register_file,
 214             sim_dump => terminate,
 215             sim_dump_done => sim_cr_dump
 216             );
 217
 218     cr_file_0: entity work.cr_file
 219         generic map (
 220             SIM => SIM
 221             )
 222         port map (
 223             clk => clk,
 224             d_in => decode2_to_cr_file,
 225             d_out => cr_file_to_decode2,
 226             w_in => writeback_to_cr_file,
 227             sim_dump => sim_cr_dump
 228             );
 229
 230     execute1_0: entity work.execute1
 231         generic map (
 232             EX1_BYPASS => EX1_BYPASS
 233             )
 234         port map (
 235             clk => clk,
 236             rst => core_rst,
 237             flush_out => flush,
 238             stall_out => ex1_stall_out,
 239             e_in => decode2_to_execute1,
 240             l_out => execute1_to_loadstore1,
 241             f_out => execute1_to_fetch1,
 242             e_out => execute1_to_writeback,
 243             icache_inval => ex1_icache_inval,
 244             terminate_out => terminate
 245             );
 246
 247     loadstore1_0: entity work.loadstore1
 248         port map (
 249             clk => clk,
 250             rst => core_rst,
 251             l_in => execute1_to_loadstore1,
 252             l_out => loadstore1_to_writeback,
 253             d_out => loadstore1_to_dcache,
 254             d_in => dcache_to_loadstore1,
 255             dc_stall => dcache_stall_out,
 256             stall_out => ls1_stall_out
 257             );
 258
 259     dcache_0: entity work.dcache
 260         generic map(
 261             LINE_SIZE => 64,
 262             NUM_LINES => 32,
 263             NUM_WAYS => 2
 264             )
 265         port map (
 266             clk => clk,
 267             rst => core_rst,
 268             d_in => loadstore1_to_dcache,
 269             d_out => dcache_to_loadstore1,
 270             stall_out => dcache_stall_out,
 271             wishbone_in => wishbone_data_in,
 272             wishbone_out => wishbone_data_out
 273             );
 274
 275     writeback_0: entity work.writeback
 276         port map (
 277             clk => clk,
 278             e_in => execute1_to_writeback,
 279             l_in => loadstore1_to_writeback,
 280             w_out => writeback_to_register_file,
 281             c_out => writeback_to_cr_file,
 282             complete_out => complete
 283             );
 284
 285     debug_0: entity work.core_debug
 286         port map (
 287             clk => clk,
 288             rst => rst,
 289             dmi_addr => dmi_addr,
 290             dmi_din => dmi_din,
 291             dmi_dout => dmi_dout,
 292             dmi_req => dmi_req,
 293             dmi_wr => dmi_wr,
 294             dmi_ack => dmi_ack,
 295             core_stop => dbg_core_stop,
 296             core_rst => dbg_core_rst,
 297             icache_rst => dbg_icache_rst,
 298             terminate => terminate,
 299             core_stopped => dbg_core_is_stopped,
 300             nia => fetch1_to_icache.nia,
 301             terminated_out => terminated_out
 302             );
 303
 304 end behave;