core.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7 use work.wishbone_types.all;
   8
   9 entity core is
  10     generic (
  11         SIM : boolean := false
  12         );
  13     port (
  14         clk          : in std_logic;
  15         rst          : in std_logic;
  16
  17         wishbone_insn_in  : in wishbone_slave_out;
  18         wishbone_insn_out : out wishbone_master_out;
  19
  20         wishbone_data_in  : in wishbone_slave_out;
  21         wishbone_data_out : out wishbone_master_out;
  22
  23         dmi_addr        : in std_ulogic_vector(3 downto 0);
  24         dmi_din         : in std_ulogic_vector(63 downto 0);
  25         dmi_dout        : out std_ulogic_vector(63 downto 0);
  26         dmi_req         : in std_ulogic;
  27         dmi_wr          : in std_ulogic;
  28         dmi_ack         : out std_ulogic;
  29
  30         terminated_out   : out std_logic
  31         );
  32 end core;
  33
  34 architecture behave of core is
  35     -- fetch signals
  36     signal fetch1_to_fetch2: Fetch1ToFetch2Type;
  37     signal fetch2_to_decode1: Fetch2ToDecode1Type;
  38
  39     -- icache signals
  40     signal fetch2_to_icache : Fetch2ToIcacheType;
  41     signal icache_to_fetch2 : IcacheToFetch2Type;
  42
  43     -- decode signals
  44     signal decode1_to_decode2: Decode1ToDecode2Type;
  45     signal decode2_to_execute1: Decode2ToExecute1Type;
  46
  47     -- register file signals
  48     signal register_file_to_decode2: RegisterFileToDecode2Type;
  49     signal decode2_to_register_file: Decode2ToRegisterFileType;
  50     signal writeback_to_register_file: WritebackToRegisterFileType;
  51
  52     -- CR file signals
  53     signal decode2_to_cr_file: Decode2ToCrFileType;
  54     signal cr_file_to_decode2: CrFileToDecode2Type;
  55     signal writeback_to_cr_file: WritebackToCrFileType;
  56
  57     -- execute signals
  58     signal execute1_to_execute2: Execute1ToExecute2Type;
  59     signal execute2_to_writeback: Execute2ToWritebackType;
  60     signal execute1_to_fetch1: Execute1ToFetch1Type;
  61
  62     -- load store signals
  63     signal decode2_to_loadstore1: Decode2ToLoadstore1Type;
  64     signal loadstore1_to_loadstore2: Loadstore1ToLoadstore2Type;
  65     signal loadstore2_to_writeback: Loadstore2ToWritebackType;
  66
  67     -- multiply signals
  68     signal decode2_to_multiply: Decode2ToMultiplyType;
  69     signal multiply_to_writeback: MultiplyToWritebackType;
  70
  71     -- divider signals
  72     signal decode2_to_divider: Decode2ToDividerType;
  73     signal divider_to_writeback: DividerToWritebackType;
  74
  75     -- local signals
  76     signal fetch1_stall_in : std_ulogic;
  77     signal fetch2_stall_in : std_ulogic;
  78     signal fetch2_stall_out : std_ulogic;
  79     signal decode1_stall_in : std_ulogic;
  80     signal decode2_stall_out : std_ulogic;
  81
  82     signal flush: std_ulogic;
  83
  84     signal complete: std_ulogic;
  85     signal terminate: std_ulogic;
  86     signal core_rst: std_ulogic;
  87     signal icache_rst: std_ulogic;
  88
  89     -- Debug actions
  90     signal dbg_core_stop: std_ulogic;
  91     signal dbg_core_rst: std_ulogic;
  92     signal dbg_icache_rst: std_ulogic;
  93
  94     -- Debug status
  95     signal dbg_core_is_stopped: std_ulogic;
  96
  97     -- For sim
  98     signal registers: regfile;
  99
 100 begin
 101
 102     core_rst <= dbg_core_rst or rst;
 103
 104     fetch1_0: entity work.fetch1
 105         generic map (
 106             RESET_ADDRESS => (others => '0')
 107             )
 108         port map (
 109             clk => clk,
 110             rst => core_rst,
 111             stall_in => fetch1_stall_in,
 112             flush_in => flush,
 113             e_in => execute1_to_fetch1,
 114             f_out => fetch1_to_fetch2
 115             );
 116
 117     fetch1_stall_in <= fetch2_stall_out or decode2_stall_out;
 118
 119     fetch2_0: entity work.fetch2
 120         port map (
 121             clk => clk,
 122             rst => core_rst,
 123             stall_in => fetch2_stall_in,
 124             stall_out => fetch2_stall_out,
 125             flush_in => flush,
 126             i_in => icache_to_fetch2,
 127             i_out => fetch2_to_icache,
 128             stop_in => dbg_core_stop,
 129             f_in => fetch1_to_fetch2,
 130             f_out => fetch2_to_decode1
 131             );
 132
 133     fetch2_stall_in <= decode2_stall_out;
 134
 135     icache_0: entity work.icache
 136         generic map(
 137             LINE_SIZE_DW => 8,
 138             NUM_LINES => 16
 139             )
 140         port map(
 141             clk => clk,
 142             rst => icache_rst,
 143             i_in => fetch2_to_icache,
 144             i_out => icache_to_fetch2,
 145             wishbone_out => wishbone_insn_out,
 146             wishbone_in => wishbone_insn_in
 147             );
 148
 149         icache_rst <= rst or dbg_icache_rst;
 150
 151     decode1_0: entity work.decode1
 152         port map (
 153             clk => clk,
 154             rst => core_rst,
 155             stall_in => decode1_stall_in,
 156             flush_in => flush,
 157             f_in => fetch2_to_decode1,
 158             d_out => decode1_to_decode2
 159             );
 160
 161     decode1_stall_in <= decode2_stall_out;
 162
 163     decode2_0: entity work.decode2
 164         port map (
 165             clk => clk,
 166             rst => core_rst,
 167             stall_out => decode2_stall_out,
 168             flush_in => flush,
 169             complete_in => complete,
 170             stopped_out => dbg_core_is_stopped,
 171             d_in => decode1_to_decode2,
 172             e_out => decode2_to_execute1,
 173             l_out => decode2_to_loadstore1,
 174             m_out => decode2_to_multiply,
 175             d_out => decode2_to_divider,
 176             r_in => register_file_to_decode2,
 177             r_out => decode2_to_register_file,
 178             c_in => cr_file_to_decode2,
 179             c_out => decode2_to_cr_file
 180             );
 181
 182     register_file_0: entity work.register_file
 183         port map (
 184             clk => clk,
 185             d_in => decode2_to_register_file,
 186             d_out => register_file_to_decode2,
 187             w_in => writeback_to_register_file,
 188             registers_out => registers);
 189
 190     cr_file_0: entity work.cr_file
 191         port map (
 192             clk => clk,
 193             d_in => decode2_to_cr_file,
 194             d_out => cr_file_to_decode2,
 195             w_in => writeback_to_cr_file
 196             );
 197
 198     execute1_0: entity work.execute1
 199         generic map (
 200             SIM => SIM
 201             )
 202         port map (
 203             clk => clk,
 204             flush_out => flush,
 205             e_in => decode2_to_execute1,
 206             f_out => execute1_to_fetch1,
 207             e_out => execute1_to_execute2,
 208             terminate_out => terminate
 209             );
 210
 211     execute2_0: entity work.execute2
 212         port map (
 213             clk => clk,
 214             e_in => execute1_to_execute2,
 215             e_out => execute2_to_writeback
 216             );
 217
 218     loadstore1_0: entity work.loadstore1
 219         port map (
 220             clk => clk,
 221             l_in => decode2_to_loadstore1,
 222             l_out => loadstore1_to_loadstore2
 223             );
 224
 225     loadstore2_0: entity work.loadstore2
 226         port map (
 227             clk => clk,
 228             l_in => loadstore1_to_loadstore2,
 229             w_out => loadstore2_to_writeback,
 230             m_in => wishbone_data_in,
 231             m_out => wishbone_data_out
 232             );
 233
 234     multiply_0: entity work.multiply
 235         port map (
 236             clk => clk,
 237             m_in => decode2_to_multiply,
 238             m_out => multiply_to_writeback
 239             );
 240
 241     divider_0: entity work.divider
 242         port map (
 243             clk => clk,
 244             rst => rst,
 245             d_in => decode2_to_divider,
 246             d_out => divider_to_writeback
 247             );
 248
 249     writeback_0: entity work.writeback
 250         port map (
 251             clk => clk,
 252             e_in => execute2_to_writeback,
 253             l_in => loadstore2_to_writeback,
 254             m_in => multiply_to_writeback,
 255             d_in => divider_to_writeback,
 256             w_out => writeback_to_register_file,
 257             c_out => writeback_to_cr_file,
 258             complete_out => complete
 259             );
 260
 261     debug_0: entity work.core_debug
 262         port map (
 263             clk => clk,
 264             rst => rst,
 265             dmi_addr => dmi_addr,
 266             dmi_din => dmi_din,
 267             dmi_dout => dmi_dout,
 268             dmi_req => dmi_req,
 269             dmi_wr => dmi_wr,
 270             dmi_ack => dmi_ack,
 271             core_stop => dbg_core_stop,
 272             core_rst => dbg_core_rst,
 273             icache_rst => dbg_icache_rst,
 274             terminate => terminate,
 275             core_stopped => dbg_core_is_stopped,
 276             nia => fetch1_to_fetch2.nia,
 277             terminated_out => terminated_out
 278             );
 279
 280     -- Dump registers if core terminates
 281     sim_terminate_test: if SIM generate
 282         dump_registers: process(all)
 283         begin
 284             if terminate = '1' then
 285                 loop_0: for i in 0 to 31 loop
 286                     report "REG " & to_hstring(registers(i));
 287                 end loop loop_0;
 288                 assert false report "end of test" severity failure;
 289             end if;
 290         end process;
 291     end generate;
 292
 293 end behave;