core.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7 use work.wishbone_types.all;
   8
   9 entity core is
  10     generic (
  11         SIM : boolean := false;
  12         DISABLE_FLATTEN : boolean := false;
  13         EX1_BYPASS : boolean := true;
  14         HAS_FPU : boolean := true;
  15         HAS_BTC : boolean := true;
  16         ALT_RESET_ADDRESS : std_ulogic_vector(63 downto 0) := (others => '0');
  17         LOG_LENGTH : natural := 512;
  18         ICACHE_NUM_LINES : natural := 64;
  19         ICACHE_NUM_WAYS : natural := 2;
  20         ICACHE_TLB_SIZE : natural := 64;
  21         DCACHE_NUM_LINES : natural := 64;
  22         DCACHE_NUM_WAYS : natural := 2;
  23         DCACHE_TLB_SET_SIZE : natural := 64;
  24         DCACHE_TLB_NUM_WAYS : natural := 2
  25         );
  26     port (
  27         clk          : in std_ulogic;
  28         rst          : in std_ulogic;
  29
  30         -- Alternate reset (0xffff0000) for use by DRAM init fw
  31         alt_reset    : in std_ulogic;
  32
  33         -- Wishbone interface
  34         wishbone_insn_in  : in wishbone_slave_out;
  35         wishbone_insn_out : out wishbone_master_out;
  36
  37         wishbone_data_in  : in wishbone_slave_out;
  38         wishbone_data_out : out wishbone_master_out;
  39
  40         wb_snoop_in     : in wishbone_master_out;
  41
  42         dmi_addr        : in std_ulogic_vector(3 downto 0);
  43         dmi_din         : in std_ulogic_vector(63 downto 0);
  44         dmi_dout        : out std_ulogic_vector(63 downto 0);
  45         dmi_req         : in std_ulogic;
  46         dmi_wr          : in std_ulogic;
  47         dmi_ack         : out std_ulogic;
  48
  49         ext_irq         : in std_ulogic;
  50
  51         terminated_out   : out std_logic
  52         );
  53 end core;
  54
  55 architecture behave of core is
  56     -- icache signals
  57     signal fetch1_to_icache : Fetch1ToIcacheType;
  58     signal writeback_to_fetch1: WritebackToFetch1Type;
  59     signal icache_to_decode1 : IcacheToDecode1Type;
  60     signal mmu_to_icache : MmuToIcacheType;
  61
  62     -- decode signals
  63     signal decode1_to_decode2: Decode1ToDecode2Type;
  64     signal decode1_to_fetch1: Decode1ToFetch1Type;
  65     signal decode2_to_execute1: Decode2ToExecute1Type;
  66
  67     -- register file signals
  68     signal register_file_to_decode2: RegisterFileToDecode2Type;
  69     signal decode2_to_register_file: Decode2ToRegisterFileType;
  70     signal writeback_to_register_file: WritebackToRegisterFileType;
  71
  72     -- CR file signals
  73     signal decode2_to_cr_file: Decode2ToCrFileType;
  74     signal cr_file_to_decode2: CrFileToDecode2Type;
  75     signal writeback_to_cr_file: WritebackToCrFileType;
  76
  77     -- execute signals
  78     signal execute1_to_writeback: Execute1ToWritebackType;
  79     signal execute1_bypass: bypass_data_t;
  80     signal execute1_cr_bypass: cr_bypass_data_t;
  81
  82     -- load store signals
  83     signal execute1_to_loadstore1: Execute1ToLoadstore1Type;
  84     signal loadstore1_to_execute1: Loadstore1ToExecute1Type;
  85     signal loadstore1_to_writeback: Loadstore1ToWritebackType;
  86     signal loadstore1_to_mmu: Loadstore1ToMmuType;
  87     signal mmu_to_loadstore1: MmuToLoadstore1Type;
  88
  89     -- dcache signals
  90     signal loadstore1_to_dcache: Loadstore1ToDcacheType;
  91     signal dcache_to_loadstore1: DcacheToLoadstore1Type;
  92     signal mmu_to_dcache: MmuToDcacheType;
  93     signal dcache_to_mmu: DcacheToMmuType;
  94
  95     -- FPU signals
  96     signal execute1_to_fpu: Execute1ToFPUType;
  97     signal fpu_to_execute1: FPUToExecute1Type;
  98     signal fpu_to_writeback: FPUToWritebackType;
  99
 100     -- local signals
 101     signal fetch1_stall_in : std_ulogic;
 102     signal icache_stall_out : std_ulogic;
 103     signal icache_stall_in : std_ulogic;
 104     signal decode1_stall_in : std_ulogic;
 105     signal decode1_busy     : std_ulogic;
 106     signal decode2_busy_in : std_ulogic;
 107     signal decode2_stall_out : std_ulogic;
 108     signal ex1_icache_inval: std_ulogic;
 109     signal ex1_busy_out: std_ulogic;
 110     signal dcache_stall_out: std_ulogic;
 111
 112     signal flush: std_ulogic;
 113     signal decode1_flush: std_ulogic;
 114     signal fetch1_flush: std_ulogic;
 115
 116     signal complete: instr_tag_t;
 117     signal terminate: std_ulogic;
 118     signal core_rst: std_ulogic;
 119     signal icache_inv: std_ulogic;
 120     signal do_interrupt: std_ulogic;
 121
 122     -- Delayed/Latched resets and alt_reset
 123     signal rst_fetch1  : std_ulogic := '1';
 124     signal rst_fetch2  : std_ulogic := '1';
 125     signal rst_icache  : std_ulogic := '1';
 126     signal rst_dcache  : std_ulogic := '1';
 127     signal rst_dec1    : std_ulogic := '1';
 128     signal rst_dec2    : std_ulogic := '1';
 129     signal rst_ex1     : std_ulogic := '1';
 130     signal rst_fpu     : std_ulogic := '1';
 131     signal rst_ls1     : std_ulogic := '1';
 132     signal rst_wback   : std_ulogic := '1';
 133     signal rst_dbg     : std_ulogic := '1';
 134     signal alt_reset_d : std_ulogic;
 135
 136     signal sim_cr_dump: std_ulogic;
 137
 138     -- Debug actions
 139     signal dbg_core_stop: std_ulogic;
 140     signal dbg_core_rst: std_ulogic;
 141     signal dbg_icache_rst: std_ulogic;
 142
 143     signal dbg_gpr_req : std_ulogic;
 144     signal dbg_gpr_ack : std_ulogic;
 145     signal dbg_gpr_addr : gspr_index_t;
 146     signal dbg_gpr_data : std_ulogic_vector(63 downto 0);
 147
 148     signal msr : std_ulogic_vector(63 downto 0);
 149
 150     -- PMU event bus
 151     signal writeback_events : WritebackEventType;
 152
 153     -- Debug status
 154     signal dbg_core_is_stopped: std_ulogic;
 155
 156     -- Logging signals
 157     signal log_data    : std_ulogic_vector(255 downto 0);
 158     signal log_rd_addr : std_ulogic_vector(31 downto 0);
 159     signal log_wr_addr : std_ulogic_vector(31 downto 0);
 160     signal log_rd_data : std_ulogic_vector(63 downto 0);
 161
 162     function keep_h(disable : boolean) return string is
 163     begin
 164         if disable then
 165             return "yes";
 166         else
 167             return "no";
 168         end if;
 169     end function;
 170     attribute keep_hierarchy : string;
 171     attribute keep_hierarchy of fetch1_0 : label is keep_h(DISABLE_FLATTEN);
 172     attribute keep_hierarchy of icache_0 : label is keep_h(DISABLE_FLATTEN);
 173     attribute keep_hierarchy of decode1_0 : label is keep_h(DISABLE_FLATTEN);
 174     attribute keep_hierarchy of decode2_0 : label is keep_h(DISABLE_FLATTEN);
 175     attribute keep_hierarchy of register_file_0 : label is keep_h(DISABLE_FLATTEN);
 176     attribute keep_hierarchy of cr_file_0 : label is keep_h(DISABLE_FLATTEN);
 177     attribute keep_hierarchy of execute1_0 : label is keep_h(DISABLE_FLATTEN);
 178     attribute keep_hierarchy of loadstore1_0 : label is keep_h(DISABLE_FLATTEN);
 179     attribute keep_hierarchy of mmu_0 : label is keep_h(DISABLE_FLATTEN);
 180     attribute keep_hierarchy of dcache_0 : label is keep_h(DISABLE_FLATTEN);
 181     attribute keep_hierarchy of writeback_0 : label is keep_h(DISABLE_FLATTEN);
 182     attribute keep_hierarchy of debug_0 : label is keep_h(DISABLE_FLATTEN);
 183 begin
 184
 185     core_rst <= dbg_core_rst or rst;
 186
 187     resets: process(clk)
 188     begin
 189         if rising_edge(clk) then
 190             rst_fetch1  <= core_rst;
 191             rst_fetch2  <= core_rst;
 192             rst_icache  <= core_rst;
 193             rst_dcache  <= core_rst;
 194             rst_dec1    <= core_rst;
 195             rst_dec2    <= core_rst;
 196             rst_ex1     <= core_rst;
 197             rst_fpu     <= core_rst;
 198             rst_ls1     <= core_rst;
 199             rst_wback   <= core_rst;
 200             rst_dbg     <= rst;
 201             alt_reset_d <= alt_reset;
 202         end if;
 203     end process;
 204
 205     fetch1_0: entity work.fetch1
 206         generic map (
 207             RESET_ADDRESS => (others => '0'),
 208             ALT_RESET_ADDRESS => ALT_RESET_ADDRESS,
 209             HAS_BTC => HAS_BTC
 210             )
 211         port map (
 212             clk => clk,
 213             rst => rst_fetch1,
 214             alt_reset_in => alt_reset_d,
 215             stall_in => fetch1_stall_in,
 216             flush_in => fetch1_flush,
 217             inval_btc => ex1_icache_inval or mmu_to_icache.tlbie,
 218             stop_in => dbg_core_stop,
 219             d_in => decode1_to_fetch1,
 220             w_in => writeback_to_fetch1,
 221             i_out => fetch1_to_icache,
 222             log_out => log_data(42 downto 0)
 223             );
 224
 225     fetch1_stall_in <= icache_stall_out or decode1_busy;
 226     fetch1_flush <= flush or decode1_flush;
 227
 228     icache_0: entity work.icache
 229         generic map(
 230             SIM => SIM,
 231             LINE_SIZE => 64,
 232             NUM_LINES => ICACHE_NUM_LINES,
 233             NUM_WAYS => ICACHE_NUM_WAYS,
 234             TLB_SIZE => ICACHE_TLB_SIZE,
 235             LOG_LENGTH => LOG_LENGTH
 236             )
 237         port map(
 238             clk => clk,
 239             rst => rst_icache,
 240             i_in => fetch1_to_icache,
 241             i_out => icache_to_decode1,
 242             m_in => mmu_to_icache,
 243             flush_in => fetch1_flush,
 244             inval_in => dbg_icache_rst or ex1_icache_inval,
 245             stall_in => icache_stall_in,
 246             stall_out => icache_stall_out,
 247             wishbone_out => wishbone_insn_out,
 248             wishbone_in => wishbone_insn_in,
 249             wb_snoop_in => wb_snoop_in,
 250             log_out => log_data(96 downto 43)
 251             );
 252
 253     icache_stall_in <= decode1_busy;
 254
 255     decode1_0: entity work.decode1
 256         generic map(
 257             HAS_FPU => HAS_FPU,
 258             LOG_LENGTH => LOG_LENGTH
 259             )
 260         port map (
 261             clk => clk,
 262             rst => rst_dec1,
 263             stall_in => decode1_stall_in,
 264             flush_in => flush,
 265             flush_out => decode1_flush,
 266             busy_out => decode1_busy,
 267             f_in => icache_to_decode1,
 268             d_out => decode1_to_decode2,
 269             f_out => decode1_to_fetch1,
 270             log_out => log_data(109 downto 97)
 271             );
 272
 273     decode1_stall_in <= decode2_stall_out;
 274
 275     decode2_0: entity work.decode2
 276         generic map (
 277             EX1_BYPASS => EX1_BYPASS,
 278             HAS_FPU => HAS_FPU,
 279             LOG_LENGTH => LOG_LENGTH
 280             )
 281         port map (
 282             clk => clk,
 283             rst => rst_dec2,
 284             busy_in => decode2_busy_in,
 285             stall_out => decode2_stall_out,
 286             flush_in => flush,
 287             complete_in => complete,
 288             stopped_out => dbg_core_is_stopped,
 289             d_in => decode1_to_decode2,
 290             e_out => decode2_to_execute1,
 291             r_in => register_file_to_decode2,
 292             r_out => decode2_to_register_file,
 293             c_in => cr_file_to_decode2,
 294             c_out => decode2_to_cr_file,
 295             execute_bypass => execute1_bypass,
 296             execute_cr_bypass => execute1_cr_bypass,
 297             log_out => log_data(119 downto 110)
 298             );
 299     decode2_busy_in <= ex1_busy_out;
 300
 301     register_file_0: entity work.register_file
 302         generic map (
 303             SIM => SIM,
 304             HAS_FPU => HAS_FPU,
 305             LOG_LENGTH => LOG_LENGTH
 306             )
 307         port map (
 308             clk => clk,
 309             d_in => decode2_to_register_file,
 310             d_out => register_file_to_decode2,
 311             w_in => writeback_to_register_file,
 312             dbg_gpr_req => dbg_gpr_req,
 313             dbg_gpr_ack => dbg_gpr_ack,
 314             dbg_gpr_addr => dbg_gpr_addr,
 315             dbg_gpr_data => dbg_gpr_data,
 316             sim_dump => terminate,
 317             sim_dump_done => sim_cr_dump,
 318             log_out => log_data(255 downto 184)
 319             );
 320
 321     cr_file_0: entity work.cr_file
 322         generic map (
 323             SIM => SIM,
 324             LOG_LENGTH => LOG_LENGTH
 325             )
 326         port map (
 327             clk => clk,
 328             d_in => decode2_to_cr_file,
 329             d_out => cr_file_to_decode2,
 330             w_in => writeback_to_cr_file,
 331             sim_dump => sim_cr_dump,
 332             log_out => log_data(183 downto 171)
 333             );
 334
 335     execute1_0: entity work.execute1
 336         generic map (
 337             EX1_BYPASS => EX1_BYPASS,
 338             HAS_FPU => HAS_FPU,
 339             LOG_LENGTH => LOG_LENGTH
 340             )
 341         port map (
 342             clk => clk,
 343             rst => rst_ex1,
 344             flush_in => flush,
 345             busy_out => ex1_busy_out,
 346             e_in => decode2_to_execute1,
 347             l_in => loadstore1_to_execute1,
 348             fp_in => fpu_to_execute1,
 349             ext_irq_in => ext_irq,
 350             interrupt_in => do_interrupt,
 351             l_out => execute1_to_loadstore1,
 352             fp_out => execute1_to_fpu,
 353             e_out => execute1_to_writeback,
 354             bypass_data => execute1_bypass,
 355             bypass_cr_data => execute1_cr_bypass,
 356             icache_inval => ex1_icache_inval,
 357             dbg_msr_out => msr,
 358             wb_events => writeback_events,
 359             terminate_out => terminate,
 360             log_out => log_data(134 downto 120),
 361             log_rd_addr => log_rd_addr,
 362             log_rd_data => log_rd_data,
 363             log_wr_addr => log_wr_addr
 364             );
 365
 366     with_fpu: if HAS_FPU generate
 367     begin
 368         fpu_0: entity work.fpu
 369             port map (
 370                 clk => clk,
 371                 rst => rst_fpu,
 372                 e_in => execute1_to_fpu,
 373                 e_out => fpu_to_execute1,
 374                 w_out => fpu_to_writeback
 375                 );
 376     end generate;
 377
 378     no_fpu: if not HAS_FPU generate
 379     begin
 380         fpu_to_execute1 <= FPUToExecute1Init;
 381         fpu_to_writeback <= FPUToWritebackInit;
 382     end generate;
 383
 384     loadstore1_0: entity work.loadstore1
 385         generic map (
 386             HAS_FPU => HAS_FPU,
 387             LOG_LENGTH => LOG_LENGTH
 388             )
 389         port map (
 390             clk => clk,
 391             rst => rst_ls1,
 392             l_in => execute1_to_loadstore1,
 393             e_out => loadstore1_to_execute1,
 394             l_out => loadstore1_to_writeback,
 395             d_out => loadstore1_to_dcache,
 396             d_in => dcache_to_loadstore1,
 397             m_out => loadstore1_to_mmu,
 398             m_in => mmu_to_loadstore1,
 399             dc_stall => dcache_stall_out,
 400             log_out => log_data(149 downto 140)
 401             );
 402
 403     mmu_0: entity work.mmu
 404         port map (
 405             clk => clk,
 406             rst => core_rst,
 407             l_in => loadstore1_to_mmu,
 408             l_out => mmu_to_loadstore1,
 409             d_out => mmu_to_dcache,
 410             d_in => dcache_to_mmu,
 411             i_out => mmu_to_icache
 412             );
 413
 414     dcache_0: entity work.dcache
 415         generic map(
 416             LINE_SIZE => 64,
 417             NUM_LINES => DCACHE_NUM_LINES,
 418             NUM_WAYS => DCACHE_NUM_WAYS,
 419             TLB_SET_SIZE => DCACHE_TLB_SET_SIZE,
 420             TLB_NUM_WAYS => DCACHE_TLB_NUM_WAYS,
 421             LOG_LENGTH => LOG_LENGTH
 422             )
 423         port map (
 424             clk => clk,
 425             rst => rst_dcache,
 426             d_in => loadstore1_to_dcache,
 427             d_out => dcache_to_loadstore1,
 428             m_in => mmu_to_dcache,
 429             m_out => dcache_to_mmu,
 430             stall_out => dcache_stall_out,
 431             wishbone_in => wishbone_data_in,
 432             wishbone_out => wishbone_data_out,
 433             snoop_in => wb_snoop_in,
 434             log_out => log_data(170 downto 151)
 435             );
 436
 437     writeback_0: entity work.writeback
 438         port map (
 439             clk => clk,
 440             rst => rst_wback,
 441             flush_out => flush,
 442             e_in => execute1_to_writeback,
 443             l_in => loadstore1_to_writeback,
 444             fp_in => fpu_to_writeback,
 445             w_out => writeback_to_register_file,
 446             c_out => writeback_to_cr_file,
 447             f_out => writeback_to_fetch1,
 448             events => writeback_events,
 449             interrupt_out => do_interrupt,
 450             complete_out => complete
 451             );
 452
 453     log_data(150) <= '0';
 454     log_data(139 downto 135) <= "00000";
 455
 456     debug_0: entity work.core_debug
 457         generic map (
 458             LOG_LENGTH => LOG_LENGTH
 459             )
 460         port map (
 461             clk => clk,
 462             rst => rst_dbg,
 463             dmi_addr => dmi_addr,
 464             dmi_din => dmi_din,
 465             dmi_dout => dmi_dout,
 466             dmi_req => dmi_req,
 467             dmi_wr => dmi_wr,
 468             dmi_ack => dmi_ack,
 469             core_stop => dbg_core_stop,
 470             core_rst => dbg_core_rst,
 471             icache_rst => dbg_icache_rst,
 472             terminate => terminate,
 473             core_stopped => dbg_core_is_stopped,
 474             nia => fetch1_to_icache.nia,
 475             msr => msr,
 476             dbg_gpr_req => dbg_gpr_req,
 477             dbg_gpr_ack => dbg_gpr_ack,
 478             dbg_gpr_addr => dbg_gpr_addr,
 479             dbg_gpr_data => dbg_gpr_data,
 480             log_data => log_data,
 481             log_read_addr => log_rd_addr,
 482             log_read_data => log_rd_data,
 483             log_write_addr => log_wr_addr,
 484             terminated_out => terminated_out
 485             );
 486
 487 end behave;