core.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7 use work.wishbone_types.all;
   8
   9 entity core is
  10     generic (
  11         SIM : boolean := false;
  12         DISABLE_FLATTEN : boolean := false;
  13         EX1_BYPASS : boolean := true
  14         );
  15     port (
  16         clk          : in std_logic;
  17         rst          : in std_logic;
  18
  19         wishbone_insn_in  : in wishbone_slave_out;
  20         wishbone_insn_out : out wishbone_master_out;
  21
  22         wishbone_data_in  : in wishbone_slave_out;
  23         wishbone_data_out : out wishbone_master_out;
  24
  25         dmi_addr        : in std_ulogic_vector(3 downto 0);
  26         dmi_din         : in std_ulogic_vector(63 downto 0);
  27         dmi_dout        : out std_ulogic_vector(63 downto 0);
  28         dmi_req         : in std_ulogic;
  29         dmi_wr          : in std_ulogic;
  30         dmi_ack         : out std_ulogic;
  31
  32         xics_in         : in XicsToExecute1Type;
  33
  34         terminated_out   : out std_logic
  35         );
  36 end core;
  37
  38 architecture behave of core is
  39     -- fetch signals
  40     signal fetch2_to_decode1: Fetch2ToDecode1Type;
  41
  42     -- icache signals
  43     signal fetch1_to_icache : Fetch1ToIcacheType;
  44     signal icache_to_fetch2 : IcacheToFetch2Type;
  45     signal mmu_to_icache : MmuToIcacheType;
  46
  47     -- decode signals
  48     signal decode1_to_decode2: Decode1ToDecode2Type;
  49     signal decode2_to_execute1: Decode2ToExecute1Type;
  50
  51     -- register file signals
  52     signal register_file_to_decode2: RegisterFileToDecode2Type;
  53     signal decode2_to_register_file: Decode2ToRegisterFileType;
  54     signal writeback_to_register_file: WritebackToRegisterFileType;
  55
  56     -- CR file signals
  57     signal decode2_to_cr_file: Decode2ToCrFileType;
  58     signal cr_file_to_decode2: CrFileToDecode2Type;
  59     signal writeback_to_cr_file: WritebackToCrFileType;
  60
  61     -- execute signals
  62     signal execute1_to_writeback: Execute1ToWritebackType;
  63     signal execute1_to_fetch1: Execute1ToFetch1Type;
  64
  65     -- load store signals
  66     signal execute1_to_loadstore1: Execute1ToLoadstore1Type;
  67     signal loadstore1_to_execute1: Loadstore1ToExecute1Type;
  68     signal loadstore1_to_writeback: Loadstore1ToWritebackType;
  69     signal loadstore1_to_mmu: Loadstore1ToMmuType;
  70     signal mmu_to_loadstore1: MmuToLoadstore1Type;
  71
  72     -- dcache signals
  73     signal loadstore1_to_dcache: Loadstore1ToDcacheType;
  74     signal dcache_to_loadstore1: DcacheToLoadstore1Type;
  75     signal mmu_to_dcache: MmuToDcacheType;
  76     signal dcache_to_mmu: DcacheToMmuType;
  77
  78     -- local signals
  79     signal fetch1_stall_in : std_ulogic;
  80     signal icache_stall_out : std_ulogic;
  81     signal fetch2_stall_in : std_ulogic;
  82     signal decode1_stall_in : std_ulogic;
  83     signal decode2_stall_in : std_ulogic;
  84     signal decode2_stall_out : std_ulogic;
  85     signal ex1_icache_inval: std_ulogic;
  86     signal ex1_stall_out: std_ulogic;
  87     signal ls1_stall_out: std_ulogic;
  88     signal dcache_stall_out: std_ulogic;
  89
  90     signal flush: std_ulogic;
  91
  92     signal complete: std_ulogic;
  93     signal terminate: std_ulogic;
  94     signal core_rst: std_ulogic;
  95     signal icache_rst: std_ulogic;
  96
  97     signal sim_cr_dump: std_ulogic;
  98
  99     -- Debug actions
 100     signal dbg_core_stop: std_ulogic;
 101     signal dbg_core_rst: std_ulogic;
 102     signal dbg_icache_rst: std_ulogic;
 103
 104     signal dbg_gpr_req : std_ulogic;
 105     signal dbg_gpr_ack : std_ulogic;
 106     signal dbg_gpr_addr : gspr_index_t;
 107     signal dbg_gpr_data : std_ulogic_vector(63 downto 0);
 108
 109     signal msr : std_ulogic_vector(63 downto 0);
 110
 111     -- Debug status
 112     signal dbg_core_is_stopped: std_ulogic;
 113
 114     function keep_h(disable : boolean) return string is
 115     begin
 116         if disable then
 117             return "yes";
 118         else
 119             return "no";
 120         end if;
 121     end function;
 122     attribute keep_hierarchy : string;
 123     attribute keep_hierarchy of fetch1_0 : label is keep_h(DISABLE_FLATTEN);
 124     attribute keep_hierarchy of icache_0 : label is keep_h(DISABLE_FLATTEN);
 125     attribute keep_hierarchy of fetch2_0 : label is keep_h(DISABLE_FLATTEN);
 126     attribute keep_hierarchy of decode1_0 : label is keep_h(DISABLE_FLATTEN);
 127     attribute keep_hierarchy of decode2_0 : label is keep_h(DISABLE_FLATTEN);
 128     attribute keep_hierarchy of register_file_0 : label is keep_h(DISABLE_FLATTEN);
 129     attribute keep_hierarchy of cr_file_0 : label is keep_h(DISABLE_FLATTEN);
 130     attribute keep_hierarchy of execute1_0 : label is keep_h(DISABLE_FLATTEN);
 131     attribute keep_hierarchy of loadstore1_0 : label is keep_h(DISABLE_FLATTEN);
 132     attribute keep_hierarchy of mmu_0 : label is keep_h(DISABLE_FLATTEN);
 133     attribute keep_hierarchy of dcache_0 : label is keep_h(DISABLE_FLATTEN);
 134     attribute keep_hierarchy of writeback_0 : label is keep_h(DISABLE_FLATTEN);
 135     attribute keep_hierarchy of debug_0 : label is keep_h(DISABLE_FLATTEN);
 136 begin
 137
 138     core_rst <= dbg_core_rst or rst;
 139
 140     fetch1_0: entity work.fetch1
 141         generic map (
 142             RESET_ADDRESS => (others => '0')
 143             )
 144         port map (
 145             clk => clk,
 146             rst => core_rst,
 147             stall_in => fetch1_stall_in,
 148             flush_in => flush,
 149             stop_in => dbg_core_stop,
 150             e_in => execute1_to_fetch1,
 151             i_out => fetch1_to_icache
 152             );
 153
 154     fetch1_stall_in <= icache_stall_out or decode2_stall_out;
 155
 156     icache_0: entity work.icache
 157         generic map(
 158             SIM => SIM,
 159             LINE_SIZE => 64,
 160             NUM_LINES => 32,
 161             NUM_WAYS => 2
 162             )
 163         port map(
 164             clk => clk,
 165             rst => icache_rst,
 166             i_in => fetch1_to_icache,
 167             i_out => icache_to_fetch2,
 168             m_in => mmu_to_icache,
 169             flush_in => flush,
 170             stall_out => icache_stall_out,
 171             wishbone_out => wishbone_insn_out,
 172             wishbone_in => wishbone_insn_in
 173             );
 174
 175     icache_rst <= rst or dbg_icache_rst or ex1_icache_inval;
 176
 177     fetch2_0: entity work.fetch2
 178         port map (
 179             clk => clk,
 180             rst => core_rst,
 181             stall_in => fetch2_stall_in,
 182             flush_in => flush,
 183             i_in => icache_to_fetch2,
 184             f_out => fetch2_to_decode1
 185             );
 186
 187     fetch2_stall_in <= decode2_stall_out;
 188
 189     decode1_0: entity work.decode1
 190         port map (
 191             clk => clk,
 192             rst => core_rst,
 193             stall_in => decode1_stall_in,
 194             flush_in => flush,
 195             f_in => fetch2_to_decode1,
 196             d_out => decode1_to_decode2
 197             );
 198
 199     decode1_stall_in <= decode2_stall_out;
 200
 201     decode2_0: entity work.decode2
 202         generic map (
 203             EX1_BYPASS => EX1_BYPASS
 204             )
 205         port map (
 206             clk => clk,
 207             rst => core_rst,
 208             stall_in => decode2_stall_in,
 209             stall_out => decode2_stall_out,
 210             flush_in => flush,
 211             complete_in => complete,
 212             stopped_out => dbg_core_is_stopped,
 213             d_in => decode1_to_decode2,
 214             e_out => decode2_to_execute1,
 215             r_in => register_file_to_decode2,
 216             r_out => decode2_to_register_file,
 217             c_in => cr_file_to_decode2,
 218             c_out => decode2_to_cr_file
 219             );
 220     decode2_stall_in <= ex1_stall_out or ls1_stall_out;
 221
 222     register_file_0: entity work.register_file
 223         generic map (
 224             SIM => SIM
 225             )
 226         port map (
 227             clk => clk,
 228             d_in => decode2_to_register_file,
 229             d_out => register_file_to_decode2,
 230             w_in => writeback_to_register_file,
 231             dbg_gpr_req => dbg_gpr_req,
 232             dbg_gpr_ack => dbg_gpr_ack,
 233             dbg_gpr_addr => dbg_gpr_addr,
 234             dbg_gpr_data => dbg_gpr_data,
 235             sim_dump => terminate,
 236             sim_dump_done => sim_cr_dump
 237             );
 238
 239     cr_file_0: entity work.cr_file
 240         generic map (
 241             SIM => SIM
 242             )
 243         port map (
 244             clk => clk,
 245             d_in => decode2_to_cr_file,
 246             d_out => cr_file_to_decode2,
 247             w_in => writeback_to_cr_file,
 248             sim_dump => sim_cr_dump
 249             );
 250
 251     execute1_0: entity work.execute1
 252         generic map (
 253             EX1_BYPASS => EX1_BYPASS
 254             )
 255         port map (
 256             clk => clk,
 257             rst => core_rst,
 258             flush_out => flush,
 259             stall_out => ex1_stall_out,
 260             e_in => decode2_to_execute1,
 261             i_in => xics_in,
 262             l_in => loadstore1_to_execute1,
 263             l_out => execute1_to_loadstore1,
 264             f_out => execute1_to_fetch1,
 265             e_out => execute1_to_writeback,
 266             icache_inval => ex1_icache_inval,
 267             dbg_msr_out => msr,
 268             terminate_out => terminate
 269             );
 270
 271     loadstore1_0: entity work.loadstore1
 272         port map (
 273             clk => clk,
 274             rst => core_rst,
 275             l_in => execute1_to_loadstore1,
 276             e_out => loadstore1_to_execute1,
 277             l_out => loadstore1_to_writeback,
 278             d_out => loadstore1_to_dcache,
 279             d_in => dcache_to_loadstore1,
 280             m_out => loadstore1_to_mmu,
 281             m_in => mmu_to_loadstore1,
 282             dc_stall => dcache_stall_out,
 283             stall_out => ls1_stall_out
 284             );
 285
 286     mmu_0: entity work.mmu
 287         port map (
 288             clk => clk,
 289             rst => core_rst,
 290             l_in => loadstore1_to_mmu,
 291             l_out => mmu_to_loadstore1,
 292             d_out => mmu_to_dcache,
 293             d_in => dcache_to_mmu,
 294             i_out => mmu_to_icache
 295             );
 296
 297     dcache_0: entity work.dcache
 298         generic map(
 299             LINE_SIZE => 64,
 300             NUM_LINES => 32,
 301             NUM_WAYS => 2
 302             )
 303         port map (
 304             clk => clk,
 305             rst => core_rst,
 306             d_in => loadstore1_to_dcache,
 307             d_out => dcache_to_loadstore1,
 308             m_in => mmu_to_dcache,
 309             m_out => dcache_to_mmu,
 310             stall_out => dcache_stall_out,
 311             wishbone_in => wishbone_data_in,
 312             wishbone_out => wishbone_data_out
 313             );
 314
 315     writeback_0: entity work.writeback
 316         port map (
 317             clk => clk,
 318             e_in => execute1_to_writeback,
 319             l_in => loadstore1_to_writeback,
 320             w_out => writeback_to_register_file,
 321             c_out => writeback_to_cr_file,
 322             complete_out => complete
 323             );
 324
 325     debug_0: entity work.core_debug
 326         port map (
 327             clk => clk,
 328             rst => rst,
 329             dmi_addr => dmi_addr,
 330             dmi_din => dmi_din,
 331             dmi_dout => dmi_dout,
 332             dmi_req => dmi_req,
 333             dmi_wr => dmi_wr,
 334             dmi_ack => dmi_ack,
 335             core_stop => dbg_core_stop,
 336             core_rst => dbg_core_rst,
 337             icache_rst => dbg_icache_rst,
 338             terminate => terminate,
 339             core_stopped => dbg_core_is_stopped,
 340             nia => fetch1_to_icache.nia,
 341             msr => msr,
 342             dbg_gpr_req => dbg_gpr_req,
 343             dbg_gpr_ack => dbg_gpr_ack,
 344             dbg_gpr_addr => dbg_gpr_addr,
 345             dbg_gpr_data => dbg_gpr_data,
 346             terminated_out => terminated_out
 347             );
 348
 349 end behave;