core.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7 use work.wishbone_types.all;
   8
   9 entity core is
  10     generic (
  11         SIM : boolean := false
  12         );
  13     port (
  14         clk          : in std_logic;
  15         rst          : in std_logic;
  16
  17         wishbone_insn_in  : in wishbone_slave_out;
  18         wishbone_insn_out : out wishbone_master_out;
  19
  20         wishbone_data_in  : in wishbone_slave_out;
  21         wishbone_data_out : out wishbone_master_out;
  22
  23         dmi_addr        : in std_ulogic_vector(3 downto 0);
  24         dmi_din         : in std_ulogic_vector(63 downto 0);
  25         dmi_dout        : out std_ulogic_vector(63 downto 0);
  26         dmi_req         : in std_ulogic;
  27         dmi_wr          : in std_ulogic;
  28         dmi_ack         : out std_ulogic;
  29
  30         terminated_out   : out std_logic
  31         );
  32 end core;
  33
  34 architecture behave of core is
  35     -- fetch signals
  36     signal fetch1_to_fetch2: Fetch1ToFetch2Type;
  37     signal fetch2_to_decode1: Fetch2ToDecode1Type;
  38
  39     -- icache signals
  40     signal fetch2_to_icache : Fetch2ToIcacheType;
  41     signal icache_to_fetch2 : IcacheToFetch2Type;
  42
  43     -- decode signals
  44     signal decode1_to_decode2: Decode1ToDecode2Type;
  45     signal decode2_to_execute1: Decode2ToExecute1Type;
  46
  47     -- register file signals
  48     signal register_file_to_decode2: RegisterFileToDecode2Type;
  49     signal decode2_to_register_file: Decode2ToRegisterFileType;
  50     signal writeback_to_register_file: WritebackToRegisterFileType;
  51
  52     -- CR file signals
  53     signal decode2_to_cr_file: Decode2ToCrFileType;
  54     signal cr_file_to_decode2: CrFileToDecode2Type;
  55     signal writeback_to_cr_file: WritebackToCrFileType;
  56
  57     -- execute signals
  58     signal execute1_to_execute2: Execute1ToExecute2Type;
  59     signal execute2_to_writeback: Execute2ToWritebackType;
  60     signal execute1_to_fetch1: Execute1ToFetch1Type;
  61
  62     -- load store signals
  63     signal decode2_to_loadstore1: Decode2ToLoadstore1Type;
  64     signal loadstore1_to_loadstore2: Loadstore1ToLoadstore2Type;
  65     signal loadstore2_to_writeback: Loadstore2ToWritebackType;
  66
  67     -- multiply signals
  68     signal decode2_to_multiply: Decode2ToMultiplyType;
  69     signal multiply_to_writeback: MultiplyToWritebackType;
  70
  71     -- local signals
  72     signal fetch1_stall_in : std_ulogic;
  73     signal fetch2_stall_in : std_ulogic;
  74     signal fetch2_stall_out : std_ulogic;
  75     signal decode1_stall_in : std_ulogic;
  76     signal decode2_stall_out : std_ulogic;
  77
  78     signal flush: std_ulogic;
  79
  80     signal complete: std_ulogic;
  81     signal terminate: std_ulogic;
  82     signal core_rst: std_ulogic;
  83     signal icache_rst: std_ulogic;
  84
  85     -- Debug actions
  86     signal dbg_core_stop: std_ulogic;
  87     signal dbg_core_rst: std_ulogic;
  88     signal dbg_icache_rst: std_ulogic;
  89
  90     -- Debug status
  91     signal dbg_core_is_stopped: std_ulogic;
  92
  93     -- For sim
  94     signal registers: regfile;
  95
  96 begin
  97
  98     core_rst <= dbg_core_rst or rst;
  99
 100     fetch1_0: entity work.fetch1
 101         generic map (
 102             RESET_ADDRESS => (others => '0')
 103             )
 104         port map (
 105             clk => clk,
 106             rst => core_rst,
 107             stall_in => fetch1_stall_in,
 108             flush_in => flush,
 109             e_in => execute1_to_fetch1,
 110             f_out => fetch1_to_fetch2
 111             );
 112
 113     fetch1_stall_in <= fetch2_stall_out or decode2_stall_out;
 114
 115     fetch2_0: entity work.fetch2
 116         port map (
 117             clk => clk,
 118             rst => core_rst,
 119             stall_in => fetch2_stall_in,
 120             stall_out => fetch2_stall_out,
 121             flush_in => flush,
 122             i_in => icache_to_fetch2,
 123             i_out => fetch2_to_icache,
 124             stop_in => dbg_core_stop,
 125             f_in => fetch1_to_fetch2,
 126             f_out => fetch2_to_decode1
 127             );
 128
 129     fetch2_stall_in <= decode2_stall_out;
 130
 131     icache_0: entity work.icache
 132         generic map(
 133             LINE_SIZE_DW => 8,
 134             NUM_LINES => 16
 135             )
 136         port map(
 137             clk => clk,
 138             rst => icache_rst,
 139             i_in => fetch2_to_icache,
 140             i_out => icache_to_fetch2,
 141             wishbone_out => wishbone_insn_out,
 142             wishbone_in => wishbone_insn_in
 143             );
 144
 145         icache_rst <= rst or dbg_icache_rst;
 146
 147     decode1_0: entity work.decode1
 148         port map (
 149             clk => clk,
 150             rst => core_rst,
 151             stall_in => decode1_stall_in,
 152             flush_in => flush,
 153             f_in => fetch2_to_decode1,
 154             d_out => decode1_to_decode2
 155             );
 156
 157     decode1_stall_in <= decode2_stall_out;
 158
 159     decode2_0: entity work.decode2
 160         port map (
 161             clk => clk,
 162             rst => core_rst,
 163             stall_out => decode2_stall_out,
 164             flush_in => flush,
 165             complete_in => complete,
 166             stopped_out => dbg_core_is_stopped,
 167             d_in => decode1_to_decode2,
 168             e_out => decode2_to_execute1,
 169             l_out => decode2_to_loadstore1,
 170             m_out => decode2_to_multiply,
 171             r_in => register_file_to_decode2,
 172             r_out => decode2_to_register_file,
 173             c_in => cr_file_to_decode2,
 174             c_out => decode2_to_cr_file
 175             );
 176
 177     register_file_0: entity work.register_file
 178         port map (
 179             clk => clk,
 180             d_in => decode2_to_register_file,
 181             d_out => register_file_to_decode2,
 182             w_in => writeback_to_register_file,
 183             registers_out => registers);
 184
 185     cr_file_0: entity work.cr_file
 186         port map (
 187             clk => clk,
 188             d_in => decode2_to_cr_file,
 189             d_out => cr_file_to_decode2,
 190             w_in => writeback_to_cr_file
 191             );
 192
 193     execute1_0: entity work.execute1
 194         generic map (
 195             SIM => SIM
 196             )
 197         port map (
 198             clk => clk,
 199             flush_out => flush,
 200             e_in => decode2_to_execute1,
 201             f_out => execute1_to_fetch1,
 202             e_out => execute1_to_execute2,
 203             terminate_out => terminate
 204             );
 205
 206     execute2_0: entity work.execute2
 207         port map (
 208             clk => clk,
 209             e_in => execute1_to_execute2,
 210             e_out => execute2_to_writeback
 211             );
 212
 213     loadstore1_0: entity work.loadstore1
 214         port map (
 215             clk => clk,
 216             l_in => decode2_to_loadstore1,
 217             l_out => loadstore1_to_loadstore2
 218             );
 219
 220     loadstore2_0: entity work.loadstore2
 221         port map (
 222             clk => clk,
 223             l_in => loadstore1_to_loadstore2,
 224             w_out => loadstore2_to_writeback,
 225             m_in => wishbone_data_in,
 226             m_out => wishbone_data_out
 227             );
 228
 229     multiply_0: entity work.multiply
 230         port map (
 231             clk => clk,
 232             m_in => decode2_to_multiply,
 233             m_out => multiply_to_writeback
 234             );
 235
 236     writeback_0: entity work.writeback
 237         port map (
 238             clk => clk,
 239             e_in => execute2_to_writeback,
 240             l_in => loadstore2_to_writeback,
 241             m_in => multiply_to_writeback,
 242             w_out => writeback_to_register_file,
 243             c_out => writeback_to_cr_file,
 244             complete_out => complete
 245             );
 246
 247     debug_0: entity work.core_debug
 248         port map (
 249             clk => clk,
 250             rst => rst,
 251             dmi_addr => dmi_addr,
 252             dmi_din => dmi_din,
 253             dmi_dout => dmi_dout,
 254             dmi_req => dmi_req,
 255             dmi_wr => dmi_wr,
 256             dmi_ack => dmi_ack,
 257             core_stop => dbg_core_stop,
 258             core_rst => dbg_core_rst,
 259             icache_rst => dbg_icache_rst,
 260             terminate => terminate,
 261             core_stopped => dbg_core_is_stopped,
 262             nia => fetch1_to_fetch2.nia,
 263             terminated_out => terminated_out
 264             );
 265
 266     -- Dump registers if core terminates
 267     sim_terminate_test: if SIM generate
 268         dump_registers: process(all)
 269         begin
 270             if terminate = '1' then
 271                 loop_0: for i in 0 to 31 loop
 272                     report "REG " & to_hstring(registers(i));
 273                 end loop loop_0;
 274                 assert false report "end of test" severity failure;
 275             end if;
 276         end process;
 277     end generate;
 278
 279 end behave;