2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
7 use work.wishbone_types.all;
11 SIM : boolean := false;
12 DISABLE_FLATTEN : boolean := false;
13 EX1_BYPASS : boolean := true;
14 HAS_FPU : boolean := true;
15 ALT_RESET_ADDRESS : std_ulogic_vector(63 downto 0) := (others => '0');
16 LOG_LENGTH : natural := 512
22 -- Alternate reset (0xffff0000) for use by DRAM init fw
23 alt_reset : in std_ulogic;
26 wishbone_insn_in : in wishbone_slave_out;
27 wishbone_insn_out : out wishbone_master_out;
29 wishbone_data_in : in wishbone_slave_out;
30 wishbone_data_out : out wishbone_master_out;
32 dmi_addr : in std_ulogic_vector(3 downto 0);
33 dmi_din : in std_ulogic_vector(63 downto 0);
34 dmi_dout : out std_ulogic_vector(63 downto 0);
35 dmi_req : in std_ulogic;
36 dmi_wr : in std_ulogic;
37 dmi_ack : out std_ulogic;
39 ext_irq : in std_ulogic;
41 terminated_out : out std_logic
45 architecture behave of core is
47 signal fetch1_to_icache : Fetch1ToIcacheType;
48 signal icache_to_decode1 : IcacheToDecode1Type;
49 signal mmu_to_icache : MmuToIcacheType;
52 signal decode1_to_decode2: Decode1ToDecode2Type;
53 signal decode1_to_fetch1: Decode1ToFetch1Type;
54 signal decode2_to_execute1: Decode2ToExecute1Type;
56 -- register file signals
57 signal register_file_to_decode2: RegisterFileToDecode2Type;
58 signal decode2_to_register_file: Decode2ToRegisterFileType;
59 signal writeback_to_register_file: WritebackToRegisterFileType;
62 signal decode2_to_cr_file: Decode2ToCrFileType;
63 signal cr_file_to_decode2: CrFileToDecode2Type;
64 signal writeback_to_cr_file: WritebackToCrFileType;
67 signal execute1_to_writeback: Execute1ToWritebackType;
68 signal execute1_to_fetch1: Execute1ToFetch1Type;
71 signal execute1_to_loadstore1: Execute1ToLoadstore1Type;
72 signal loadstore1_to_execute1: Loadstore1ToExecute1Type;
73 signal loadstore1_to_writeback: Loadstore1ToWritebackType;
74 signal loadstore1_to_mmu: Loadstore1ToMmuType;
75 signal mmu_to_loadstore1: MmuToLoadstore1Type;
78 signal loadstore1_to_dcache: Loadstore1ToDcacheType;
79 signal dcache_to_loadstore1: DcacheToLoadstore1Type;
80 signal mmu_to_dcache: MmuToDcacheType;
81 signal dcache_to_mmu: DcacheToMmuType;
84 signal execute1_to_fpu: Execute1ToFPUType;
85 signal fpu_to_execute1: FPUToExecute1Type;
86 signal fpu_to_writeback: FPUToWritebackType;
89 signal fetch1_stall_in : std_ulogic;
90 signal icache_stall_out : std_ulogic;
91 signal icache_stall_in : std_ulogic;
92 signal decode1_stall_in : std_ulogic;
93 signal decode1_busy : std_ulogic;
94 signal decode2_busy_in : std_ulogic;
95 signal decode2_stall_out : std_ulogic;
96 signal ex1_icache_inval: std_ulogic;
97 signal ex1_busy_out: std_ulogic;
98 signal dcache_stall_out: std_ulogic;
100 signal flush: std_ulogic;
101 signal decode1_flush: std_ulogic;
102 signal fetch1_flush: std_ulogic;
104 signal complete: std_ulogic;
105 signal terminate: std_ulogic;
106 signal core_rst: std_ulogic;
107 signal icache_inv: std_ulogic;
109 -- Delayed/Latched resets and alt_reset
110 signal rst_fetch1 : std_ulogic := '1';
111 signal rst_fetch2 : std_ulogic := '1';
112 signal rst_icache : std_ulogic := '1';
113 signal rst_dcache : std_ulogic := '1';
114 signal rst_dec1 : std_ulogic := '1';
115 signal rst_dec2 : std_ulogic := '1';
116 signal rst_ex1 : std_ulogic := '1';
117 signal rst_fpu : std_ulogic := '1';
118 signal rst_ls1 : std_ulogic := '1';
119 signal rst_dbg : std_ulogic := '1';
120 signal alt_reset_d : std_ulogic;
122 signal sim_cr_dump: std_ulogic;
125 signal dbg_core_stop: std_ulogic;
126 signal dbg_core_rst: std_ulogic;
127 signal dbg_icache_rst: std_ulogic;
129 signal dbg_gpr_req : std_ulogic;
130 signal dbg_gpr_ack : std_ulogic;
131 signal dbg_gpr_addr : gspr_index_t;
132 signal dbg_gpr_data : std_ulogic_vector(63 downto 0);
134 signal msr : std_ulogic_vector(63 downto 0);
137 signal dbg_core_is_stopped: std_ulogic;
140 signal log_data : std_ulogic_vector(255 downto 0);
141 signal log_rd_addr : std_ulogic_vector(31 downto 0);
142 signal log_wr_addr : std_ulogic_vector(31 downto 0);
143 signal log_rd_data : std_ulogic_vector(63 downto 0);
145 function keep_h(disable : boolean) return string is
153 attribute keep_hierarchy : string;
154 attribute keep_hierarchy of fetch1_0 : label is keep_h(DISABLE_FLATTEN);
155 attribute keep_hierarchy of icache_0 : label is keep_h(DISABLE_FLATTEN);
156 attribute keep_hierarchy of decode1_0 : label is keep_h(DISABLE_FLATTEN);
157 attribute keep_hierarchy of decode2_0 : label is keep_h(DISABLE_FLATTEN);
158 attribute keep_hierarchy of register_file_0 : label is keep_h(DISABLE_FLATTEN);
159 attribute keep_hierarchy of cr_file_0 : label is keep_h(DISABLE_FLATTEN);
160 attribute keep_hierarchy of execute1_0 : label is keep_h(DISABLE_FLATTEN);
161 attribute keep_hierarchy of loadstore1_0 : label is keep_h(DISABLE_FLATTEN);
162 attribute keep_hierarchy of mmu_0 : label is keep_h(DISABLE_FLATTEN);
163 attribute keep_hierarchy of dcache_0 : label is keep_h(DISABLE_FLATTEN);
164 attribute keep_hierarchy of writeback_0 : label is keep_h(DISABLE_FLATTEN);
165 attribute keep_hierarchy of debug_0 : label is keep_h(DISABLE_FLATTEN);
168 core_rst <= dbg_core_rst or rst;
172 if rising_edge(clk) then
173 rst_fetch1 <= core_rst;
174 rst_fetch2 <= core_rst;
175 rst_icache <= core_rst;
176 rst_dcache <= core_rst;
177 rst_dec1 <= core_rst;
178 rst_dec2 <= core_rst;
183 alt_reset_d <= alt_reset;
187 fetch1_0: entity work.fetch1
189 RESET_ADDRESS => (others => '0'),
190 ALT_RESET_ADDRESS => ALT_RESET_ADDRESS
195 alt_reset_in => alt_reset_d,
196 stall_in => fetch1_stall_in,
197 flush_in => fetch1_flush,
198 stop_in => dbg_core_stop,
199 d_in => decode1_to_fetch1,
200 e_in => execute1_to_fetch1,
201 i_out => fetch1_to_icache,
202 log_out => log_data(42 downto 0)
205 fetch1_stall_in <= icache_stall_out or decode1_busy;
206 fetch1_flush <= flush or decode1_flush;
208 icache_0: entity work.icache
214 LOG_LENGTH => LOG_LENGTH
219 i_in => fetch1_to_icache,
220 i_out => icache_to_decode1,
221 m_in => mmu_to_icache,
222 flush_in => fetch1_flush,
223 inval_in => dbg_icache_rst or ex1_icache_inval,
224 stall_in => icache_stall_in,
225 stall_out => icache_stall_out,
226 wishbone_out => wishbone_insn_out,
227 wishbone_in => wishbone_insn_in,
228 log_out => log_data(96 downto 43)
231 icache_stall_in <= decode1_busy;
233 decode1_0: entity work.decode1
236 LOG_LENGTH => LOG_LENGTH
241 stall_in => decode1_stall_in,
243 flush_out => decode1_flush,
244 busy_out => decode1_busy,
245 f_in => icache_to_decode1,
246 d_out => decode1_to_decode2,
247 f_out => decode1_to_fetch1,
248 log_out => log_data(109 downto 97)
251 decode1_stall_in <= decode2_stall_out;
253 decode2_0: entity work.decode2
255 EX1_BYPASS => EX1_BYPASS,
257 LOG_LENGTH => LOG_LENGTH
262 busy_in => decode2_busy_in,
263 stall_out => decode2_stall_out,
265 complete_in => complete,
266 stopped_out => dbg_core_is_stopped,
267 d_in => decode1_to_decode2,
268 e_out => decode2_to_execute1,
269 r_in => register_file_to_decode2,
270 r_out => decode2_to_register_file,
271 c_in => cr_file_to_decode2,
272 c_out => decode2_to_cr_file,
273 log_out => log_data(119 downto 110)
275 decode2_busy_in <= ex1_busy_out;
277 register_file_0: entity work.register_file
281 LOG_LENGTH => LOG_LENGTH
285 d_in => decode2_to_register_file,
286 d_out => register_file_to_decode2,
287 w_in => writeback_to_register_file,
288 dbg_gpr_req => dbg_gpr_req,
289 dbg_gpr_ack => dbg_gpr_ack,
290 dbg_gpr_addr => dbg_gpr_addr,
291 dbg_gpr_data => dbg_gpr_data,
292 sim_dump => terminate,
293 sim_dump_done => sim_cr_dump,
294 log_out => log_data(255 downto 184)
297 cr_file_0: entity work.cr_file
300 LOG_LENGTH => LOG_LENGTH
304 d_in => decode2_to_cr_file,
305 d_out => cr_file_to_decode2,
306 w_in => writeback_to_cr_file,
307 sim_dump => sim_cr_dump,
308 log_out => log_data(183 downto 171)
311 execute1_0: entity work.execute1
313 EX1_BYPASS => EX1_BYPASS,
315 LOG_LENGTH => LOG_LENGTH
321 busy_out => ex1_busy_out,
322 e_in => decode2_to_execute1,
323 l_in => loadstore1_to_execute1,
324 fp_in => fpu_to_execute1,
325 ext_irq_in => ext_irq,
326 l_out => execute1_to_loadstore1,
327 f_out => execute1_to_fetch1,
328 fp_out => execute1_to_fpu,
329 e_out => execute1_to_writeback,
330 icache_inval => ex1_icache_inval,
332 terminate_out => terminate,
333 log_out => log_data(134 downto 120),
334 log_rd_addr => log_rd_addr,
335 log_rd_data => log_rd_data,
336 log_wr_addr => log_wr_addr
339 with_fpu: if HAS_FPU generate
341 fpu_0: entity work.fpu
345 e_in => execute1_to_fpu,
346 e_out => fpu_to_execute1,
347 w_out => fpu_to_writeback
351 no_fpu: if not HAS_FPU generate
353 fpu_to_execute1 <= FPUToExecute1Init;
354 fpu_to_writeback <= FPUToWritebackInit;
357 loadstore1_0: entity work.loadstore1
360 LOG_LENGTH => LOG_LENGTH
365 l_in => execute1_to_loadstore1,
366 e_out => loadstore1_to_execute1,
367 l_out => loadstore1_to_writeback,
368 d_out => loadstore1_to_dcache,
369 d_in => dcache_to_loadstore1,
370 m_out => loadstore1_to_mmu,
371 m_in => mmu_to_loadstore1,
372 dc_stall => dcache_stall_out,
373 log_out => log_data(149 downto 140)
376 mmu_0: entity work.mmu
380 l_in => loadstore1_to_mmu,
381 l_out => mmu_to_loadstore1,
382 d_out => mmu_to_dcache,
383 d_in => dcache_to_mmu,
384 i_out => mmu_to_icache
387 dcache_0: entity work.dcache
392 LOG_LENGTH => LOG_LENGTH
397 d_in => loadstore1_to_dcache,
398 d_out => dcache_to_loadstore1,
399 m_in => mmu_to_dcache,
400 m_out => dcache_to_mmu,
401 stall_out => dcache_stall_out,
402 wishbone_in => wishbone_data_in,
403 wishbone_out => wishbone_data_out,
404 log_out => log_data(170 downto 151)
407 writeback_0: entity work.writeback
410 e_in => execute1_to_writeback,
411 l_in => loadstore1_to_writeback,
412 fp_in => fpu_to_writeback,
413 w_out => writeback_to_register_file,
414 c_out => writeback_to_cr_file,
415 complete_out => complete
418 log_data(150) <= '0';
419 log_data(139 downto 135) <= "00000";
421 debug_0: entity work.core_debug
423 LOG_LENGTH => LOG_LENGTH
428 dmi_addr => dmi_addr,
430 dmi_dout => dmi_dout,
434 core_stop => dbg_core_stop,
435 core_rst => dbg_core_rst,
436 icache_rst => dbg_icache_rst,
437 terminate => terminate,
438 core_stopped => dbg_core_is_stopped,
439 nia => fetch1_to_icache.nia,
441 dbg_gpr_req => dbg_gpr_req,
442 dbg_gpr_ack => dbg_gpr_ack,
443 dbg_gpr_addr => dbg_gpr_addr,
444 dbg_gpr_data => dbg_gpr_data,
445 log_data => log_data,
446 log_read_addr => log_rd_addr,
447 log_read_data => log_rd_data,
448 log_write_addr => log_wr_addr,
449 terminated_out => terminated_out