2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
7 use work.wishbone_types.all;
11 SIM : boolean := false
17 wishbone_insn_in : in wishbone_slave_out;
18 wishbone_insn_out : out wishbone_master_out;
20 wishbone_data_in : in wishbone_slave_out;
21 wishbone_data_out : out wishbone_master_out;
23 dmi_addr : in std_ulogic_vector(3 downto 0);
24 dmi_din : in std_ulogic_vector(63 downto 0);
25 dmi_dout : out std_ulogic_vector(63 downto 0);
26 dmi_req : in std_ulogic;
27 dmi_wr : in std_ulogic;
28 dmi_ack : out std_ulogic;
30 terminated_out : out std_logic
34 architecture behave of core is
36 signal fetch2_to_decode1: Fetch2ToDecode1Type;
39 signal fetch1_to_icache : Fetch1ToIcacheType;
40 signal icache_to_fetch2 : IcacheToFetch2Type;
43 signal decode1_to_decode2: Decode1ToDecode2Type;
44 signal decode2_to_execute1: Decode2ToExecute1Type;
46 -- register file signals
47 signal register_file_to_decode2: RegisterFileToDecode2Type;
48 signal decode2_to_register_file: Decode2ToRegisterFileType;
49 signal writeback_to_register_file: WritebackToRegisterFileType;
52 signal decode2_to_cr_file: Decode2ToCrFileType;
53 signal cr_file_to_decode2: CrFileToDecode2Type;
54 signal writeback_to_cr_file: WritebackToCrFileType;
57 signal execute1_to_writeback: Execute1ToWritebackType;
58 signal execute1_to_fetch1: Execute1ToFetch1Type;
61 signal decode2_to_loadstore1: Decode2ToLoadstore1Type;
62 signal loadstore1_to_loadstore2: Loadstore1ToLoadstore2Type;
63 signal loadstore2_to_writeback: Loadstore2ToWritebackType;
66 signal decode2_to_multiply: Decode2ToMultiplyType;
67 signal multiply_to_writeback: MultiplyToWritebackType;
70 signal decode2_to_divider: Decode2ToDividerType;
71 signal divider_to_writeback: DividerToWritebackType;
74 signal fetch1_stall_in : std_ulogic;
75 signal icache_stall_out : std_ulogic;
76 signal fetch2_stall_in : std_ulogic;
77 signal decode1_stall_in : std_ulogic;
78 signal decode2_stall_out : std_ulogic;
80 signal flush: std_ulogic;
82 signal complete: std_ulogic;
83 signal terminate: std_ulogic;
84 signal core_rst: std_ulogic;
85 signal icache_rst: std_ulogic;
88 signal dbg_core_stop: std_ulogic;
89 signal dbg_core_rst: std_ulogic;
90 signal dbg_icache_rst: std_ulogic;
93 signal dbg_core_is_stopped: std_ulogic;
97 core_rst <= dbg_core_rst or rst;
99 fetch1_0: entity work.fetch1
101 RESET_ADDRESS => (others => '0')
106 stall_in => fetch1_stall_in,
108 stop_in => dbg_core_stop,
109 e_in => execute1_to_fetch1,
110 i_out => fetch1_to_icache
113 fetch1_stall_in <= icache_stall_out or decode2_stall_out;
115 icache_0: entity work.icache
124 i_in => fetch1_to_icache,
125 i_out => icache_to_fetch2,
127 stall_out => icache_stall_out,
128 wishbone_out => wishbone_insn_out,
129 wishbone_in => wishbone_insn_in
132 icache_rst <= rst or dbg_icache_rst;
134 fetch2_0: entity work.fetch2
138 stall_in => fetch2_stall_in,
140 i_in => icache_to_fetch2,
141 f_out => fetch2_to_decode1
144 fetch2_stall_in <= decode2_stall_out;
146 decode1_0: entity work.decode1
150 stall_in => decode1_stall_in,
152 f_in => fetch2_to_decode1,
153 d_out => decode1_to_decode2
156 decode1_stall_in <= decode2_stall_out;
158 decode2_0: entity work.decode2
162 stall_out => decode2_stall_out,
164 complete_in => complete,
165 stopped_out => dbg_core_is_stopped,
166 d_in => decode1_to_decode2,
167 e_out => decode2_to_execute1,
168 l_out => decode2_to_loadstore1,
169 m_out => decode2_to_multiply,
170 d_out => decode2_to_divider,
171 r_in => register_file_to_decode2,
172 r_out => decode2_to_register_file,
173 c_in => cr_file_to_decode2,
174 c_out => decode2_to_cr_file
177 register_file_0: entity work.register_file
183 d_in => decode2_to_register_file,
184 d_out => register_file_to_decode2,
185 w_in => writeback_to_register_file,
186 sim_dump => terminate
189 cr_file_0: entity work.cr_file
192 d_in => decode2_to_cr_file,
193 d_out => cr_file_to_decode2,
194 w_in => writeback_to_cr_file
197 execute1_0: entity work.execute1
204 e_in => decode2_to_execute1,
205 f_out => execute1_to_fetch1,
206 e_out => execute1_to_writeback,
207 terminate_out => terminate
210 loadstore1_0: entity work.loadstore1
213 l_in => decode2_to_loadstore1,
214 l_out => loadstore1_to_loadstore2
217 loadstore2_0: entity work.loadstore2
220 l_in => loadstore1_to_loadstore2,
221 w_out => loadstore2_to_writeback,
222 m_in => wishbone_data_in,
223 m_out => wishbone_data_out
226 multiply_0: entity work.multiply
229 m_in => decode2_to_multiply,
230 m_out => multiply_to_writeback
233 divider_0: entity work.divider
237 d_in => decode2_to_divider,
238 d_out => divider_to_writeback
241 writeback_0: entity work.writeback
244 e_in => execute1_to_writeback,
245 l_in => loadstore2_to_writeback,
246 m_in => multiply_to_writeback,
247 d_in => divider_to_writeback,
248 w_out => writeback_to_register_file,
249 c_out => writeback_to_cr_file,
250 complete_out => complete
253 debug_0: entity work.core_debug
257 dmi_addr => dmi_addr,
259 dmi_dout => dmi_dout,
263 core_stop => dbg_core_stop,
264 core_rst => dbg_core_rst,
265 icache_rst => dbg_icache_rst,
266 terminate => terminate,
267 core_stopped => dbg_core_is_stopped,
268 nia => fetch1_to_icache.nia,
269 terminated_out => terminated_out