2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
7 use work.wishbone_types.all;
11 SIM : boolean := false;
12 DISABLE_FLATTEN : boolean := false;
13 EX1_BYPASS : boolean := true;
14 ALT_RESET_ADDRESS : std_ulogic_vector(63 downto 0) := (others => '0')
20 -- Alternate reset (0xffff0000) for use by DRAM init fw
21 alt_reset : in std_ulogic;
24 wishbone_insn_in : in wishbone_slave_out;
25 wishbone_insn_out : out wishbone_master_out;
27 wishbone_data_in : in wishbone_slave_out;
28 wishbone_data_out : out wishbone_master_out;
30 dmi_addr : in std_ulogic_vector(3 downto 0);
31 dmi_din : in std_ulogic_vector(63 downto 0);
32 dmi_dout : out std_ulogic_vector(63 downto 0);
33 dmi_req : in std_ulogic;
34 dmi_wr : in std_ulogic;
35 dmi_ack : out std_ulogic;
37 xics_in : in XicsToExecute1Type;
39 terminated_out : out std_logic
43 architecture behave of core is
45 signal fetch2_to_decode1: Fetch2ToDecode1Type;
48 signal fetch1_to_icache : Fetch1ToIcacheType;
49 signal icache_to_fetch2 : IcacheToFetch2Type;
52 signal decode1_to_decode2: Decode1ToDecode2Type;
53 signal decode2_to_execute1: Decode2ToExecute1Type;
55 -- register file signals
56 signal register_file_to_decode2: RegisterFileToDecode2Type;
57 signal decode2_to_register_file: Decode2ToRegisterFileType;
58 signal writeback_to_register_file: WritebackToRegisterFileType;
61 signal decode2_to_cr_file: Decode2ToCrFileType;
62 signal cr_file_to_decode2: CrFileToDecode2Type;
63 signal writeback_to_cr_file: WritebackToCrFileType;
66 signal execute1_to_writeback: Execute1ToWritebackType;
67 signal execute1_to_fetch1: Execute1ToFetch1Type;
70 signal execute1_to_loadstore1: Execute1ToLoadstore1Type;
71 signal loadstore1_to_writeback: Loadstore1ToWritebackType;
74 signal loadstore1_to_dcache: Loadstore1ToDcacheType;
75 signal dcache_to_loadstore1: DcacheToLoadstore1Type;
78 signal fetch1_stall_in : std_ulogic;
79 signal icache_stall_out : std_ulogic;
80 signal fetch2_stall_in : std_ulogic;
81 signal decode1_stall_in : std_ulogic;
82 signal decode2_stall_in : std_ulogic;
83 signal decode2_stall_out : std_ulogic;
84 signal ex1_icache_inval: std_ulogic;
85 signal ex1_stall_out: std_ulogic;
86 signal ls1_stall_out: std_ulogic;
87 signal dcache_stall_out: std_ulogic;
89 signal flush: std_ulogic;
91 signal complete: std_ulogic;
92 signal terminate: std_ulogic;
93 signal core_rst: std_ulogic;
94 signal icache_rst: std_ulogic;
96 signal sim_cr_dump: std_ulogic;
99 signal dbg_core_stop: std_ulogic;
100 signal dbg_core_rst: std_ulogic;
101 signal dbg_icache_rst: std_ulogic;
104 signal dbg_core_is_stopped: std_ulogic;
106 function keep_h(disable : boolean) return string is
114 attribute keep_hierarchy : string;
115 attribute keep_hierarchy of fetch1_0 : label is keep_h(DISABLE_FLATTEN);
116 attribute keep_hierarchy of icache_0 : label is keep_h(DISABLE_FLATTEN);
117 attribute keep_hierarchy of fetch2_0 : label is keep_h(DISABLE_FLATTEN);
118 attribute keep_hierarchy of decode1_0 : label is keep_h(DISABLE_FLATTEN);
119 attribute keep_hierarchy of decode2_0 : label is keep_h(DISABLE_FLATTEN);
120 attribute keep_hierarchy of register_file_0 : label is keep_h(DISABLE_FLATTEN);
121 attribute keep_hierarchy of cr_file_0 : label is keep_h(DISABLE_FLATTEN);
122 attribute keep_hierarchy of execute1_0 : label is keep_h(DISABLE_FLATTEN);
123 attribute keep_hierarchy of loadstore1_0 : label is keep_h(DISABLE_FLATTEN);
124 attribute keep_hierarchy of dcache_0 : label is keep_h(DISABLE_FLATTEN);
125 attribute keep_hierarchy of writeback_0 : label is keep_h(DISABLE_FLATTEN);
126 attribute keep_hierarchy of debug_0 : label is keep_h(DISABLE_FLATTEN);
129 core_rst <= dbg_core_rst or rst;
131 fetch1_0: entity work.fetch1
133 RESET_ADDRESS => (others => '0'),
134 ALT_RESET_ADDRESS => ALT_RESET_ADDRESS
139 alt_reset_in => alt_reset,
140 stall_in => fetch1_stall_in,
142 stop_in => dbg_core_stop,
143 e_in => execute1_to_fetch1,
144 i_out => fetch1_to_icache
147 fetch1_stall_in <= icache_stall_out or decode2_stall_out;
149 icache_0: entity work.icache
159 i_in => fetch1_to_icache,
160 i_out => icache_to_fetch2,
162 stall_out => icache_stall_out,
163 wishbone_out => wishbone_insn_out,
164 wishbone_in => wishbone_insn_in
167 icache_rst <= rst or dbg_icache_rst or ex1_icache_inval;
169 fetch2_0: entity work.fetch2
173 stall_in => fetch2_stall_in,
175 i_in => icache_to_fetch2,
176 f_out => fetch2_to_decode1
179 fetch2_stall_in <= decode2_stall_out;
181 decode1_0: entity work.decode1
185 stall_in => decode1_stall_in,
187 f_in => fetch2_to_decode1,
188 d_out => decode1_to_decode2
191 decode1_stall_in <= decode2_stall_out;
193 decode2_0: entity work.decode2
195 EX1_BYPASS => EX1_BYPASS
200 stall_in => decode2_stall_in,
201 stall_out => decode2_stall_out,
203 complete_in => complete,
204 stopped_out => dbg_core_is_stopped,
205 d_in => decode1_to_decode2,
206 e_out => decode2_to_execute1,
207 r_in => register_file_to_decode2,
208 r_out => decode2_to_register_file,
209 c_in => cr_file_to_decode2,
210 c_out => decode2_to_cr_file
212 decode2_stall_in <= ex1_stall_out or ls1_stall_out;
214 register_file_0: entity work.register_file
220 d_in => decode2_to_register_file,
221 d_out => register_file_to_decode2,
222 w_in => writeback_to_register_file,
223 sim_dump => terminate,
224 sim_dump_done => sim_cr_dump
227 cr_file_0: entity work.cr_file
233 d_in => decode2_to_cr_file,
234 d_out => cr_file_to_decode2,
235 w_in => writeback_to_cr_file,
236 sim_dump => sim_cr_dump
239 execute1_0: entity work.execute1
241 EX1_BYPASS => EX1_BYPASS
247 stall_out => ex1_stall_out,
248 e_in => decode2_to_execute1,
250 l_out => execute1_to_loadstore1,
251 f_out => execute1_to_fetch1,
252 e_out => execute1_to_writeback,
253 icache_inval => ex1_icache_inval,
254 terminate_out => terminate
257 loadstore1_0: entity work.loadstore1
261 l_in => execute1_to_loadstore1,
262 l_out => loadstore1_to_writeback,
263 d_out => loadstore1_to_dcache,
264 d_in => dcache_to_loadstore1,
265 dc_stall => dcache_stall_out,
266 stall_out => ls1_stall_out
269 dcache_0: entity work.dcache
278 d_in => loadstore1_to_dcache,
279 d_out => dcache_to_loadstore1,
280 stall_out => dcache_stall_out,
281 wishbone_in => wishbone_data_in,
282 wishbone_out => wishbone_data_out
285 writeback_0: entity work.writeback
288 e_in => execute1_to_writeback,
289 l_in => loadstore1_to_writeback,
290 w_out => writeback_to_register_file,
291 c_out => writeback_to_cr_file,
292 complete_out => complete
295 debug_0: entity work.core_debug
299 dmi_addr => dmi_addr,
301 dmi_dout => dmi_dout,
305 core_stop => dbg_core_stop,
306 core_rst => dbg_core_rst,
307 icache_rst => dbg_icache_rst,
308 terminate => terminate,
309 core_stopped => dbg_core_is_stopped,
310 nia => fetch1_to_icache.nia,
311 terminated_out => terminated_out