2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
13 dmi_addr : in std_ulogic_vector(3 downto 0);
14 dmi_din : in std_ulogic_vector(63 downto 0);
15 dmi_dout : out std_ulogic_vector(63 downto 0);
16 dmi_req : in std_ulogic;
17 dmi_wr : in std_ulogic;
18 dmi_ack : out std_ulogic;
21 core_stop : out std_ulogic;
22 core_rst : out std_ulogic;
23 icache_rst : out std_ulogic;
26 terminate : in std_ulogic;
27 core_stopped : in std_ulogic;
28 nia : in std_ulogic_vector(63 downto 0);
31 terminated_out : out std_ulogic
35 architecture behave of core_debug is
36 -- DMI needs fixing... make a one clock pulse
37 signal dmi_req_1: std_ulogic;
39 -- CTRL register (direct actions, write 1 to act, read back 0)
41 -- bit 1 : Core reset (doesn't clear stop)
42 -- bit 2 : Icache reset
43 -- bit 3 : Single step
45 constant DBG_CORE_CTRL : std_ulogic_vector(3 downto 0) := "0000";
46 constant DBG_CORE_CTRL_STOP : integer := 0;
47 constant DBG_CORE_CTRL_RESET : integer := 1;
48 constant DBG_CORE_CTRL_ICRESET : integer := 2;
49 constant DBG_CORE_CTRL_STEP : integer := 3;
50 constant DBG_CORE_CTRL_START : integer := 4;
52 -- STAT register (read only)
53 -- bit 0 : Core stopping (wait til bit 1 set)
54 -- bit 1 : Core stopped
55 -- bit 2 : Core terminated (clears with start or reset)
56 constant DBG_CORE_STAT : std_ulogic_vector(3 downto 0) := "0001";
57 constant DBG_CORE_STAT_STOPPING : integer := 0;
58 constant DBG_CORE_STAT_STOPPED : integer := 1;
59 constant DBG_CORE_STAT_TERM : integer := 2;
61 -- NIA register (read only for now)
62 constant DBG_CORE_NIA : std_ulogic_vector(3 downto 0) := "0010";
64 -- Some internal wires
65 signal stat_reg : std_ulogic_vector(63 downto 0);
67 -- Some internal latches
68 signal stopping : std_ulogic;
69 signal do_step : std_ulogic;
70 signal do_reset : std_ulogic;
71 signal do_icreset : std_ulogic;
72 signal terminated : std_ulogic;
75 -- Single cycle register accesses on DMI
78 -- Status register read composition
79 stat_reg <= (2 => terminated,
85 with dmi_addr select dmi_dout <=
86 stat_reg when DBG_CORE_STAT,
87 nia when DBG_CORE_NIA,
88 (others => '0') when others;
91 reg_write: process(clk)
93 if rising_edge(clk) then
98 -- Reset the 1-cycle "do" signals
103 -- Edge detect on dmi_req for 1-shot pulses
104 dmi_req_1 <= dmi_req;
105 if dmi_req = '1' and dmi_req_1 = '0' then
107 report("DMI write to " & to_hstring(dmi_addr));
109 -- Control register actions
110 if dmi_addr = DBG_CORE_CTRL then
111 if dmi_din(DBG_CORE_CTRL_RESET) = '1' then
115 if dmi_din(DBG_CORE_CTRL_STOP) = '1' then
118 if dmi_din(DBG_CORE_CTRL_STEP) = '1' then
122 if dmi_din(DBG_CORE_CTRL_ICRESET) = '1' then
125 if dmi_din(DBG_CORE_CTRL_START) = '1' then
131 report("DMI read from " & to_string(dmi_addr));
135 -- Set core stop on terminate. We'll be stopping some time *after*
136 -- the offending instruction, at least until we can do back flushes
137 -- that preserve NIA which we can't just yet.
138 if terminate = '1' then
146 -- Core control signals generated by the debug module
147 core_stop <= stopping and not do_step;
148 core_rst <= do_reset;
149 icache_rst <= do_icreset;
150 terminated_out <= terminated;