2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
7 use work.wishbone_types.all;
11 MEMORY_SIZE : natural := (384*1024);
12 MAIN_RAM_FILE : string := "main_ram.bin";
13 DRAM_INIT_FILE : string := "";
14 DRAM_INIT_SIZE : natural := 16#c000#
18 architecture behave of core_dram_tb is
19 signal clk, rst: std_logic;
20 signal system_clk, soc_rst : std_ulogic;
23 constant clk_period : time := 10 ns;
26 signal wb_dram_in : wishbone_master_out;
27 signal wb_dram_out : wishbone_slave_out;
28 signal wb_dram_ctrl_in : wb_io_master_out;
29 signal wb_dram_ctrl_out : wb_io_slave_out;
30 signal wb_dram_is_csr : std_ulogic;
31 signal wb_dram_is_init : std_ulogic;
32 signal core_alt_reset : std_ulogic;
35 function get_rom_size return natural is
37 if MEMORY_SIZE = 0 then
38 return DRAM_INIT_SIZE;
44 constant ROM_SIZE : natural := get_rom_size;
50 MEMORY_SIZE => MEMORY_SIZE,
51 RAM_INIT_FILE => MAIN_RAM_FILE,
54 DRAM_SIZE => 256 * 1024 * 1024,
55 DRAM_INIT_SIZE => ROM_SIZE,
60 system_clk => system_clk,
63 wb_dram_in => wb_dram_in,
64 wb_dram_out => wb_dram_out,
65 wb_dram_ctrl_in => wb_dram_ctrl_in,
66 wb_dram_ctrl_out => wb_dram_ctrl_out,
67 wb_dram_is_csr => wb_dram_is_csr,
68 wb_dram_is_init => wb_dram_is_init,
69 alt_reset => core_alt_reset
72 dram: entity work.litedram_wrapper
76 PAYLOAD_FILE => DRAM_INIT_FILE,
77 PAYLOAD_SIZE => ROM_SIZE
82 system_clk => system_clk,
83 system_reset => soc_rst,
84 core_alt_reset => core_alt_reset,
88 wb_out => wb_dram_out,
89 wb_ctrl_in => wb_dram_ctrl_in,
90 wb_ctrl_out => wb_dram_ctrl_out,
91 wb_ctrl_is_csr => wb_dram_is_csr,
92 wb_ctrl_is_init => wb_dram_is_init,
114 ddram_reset_n => open
120 wait for clk_period/2;
122 wait for clk_period/2;
128 wait for 10*clk_period;
133 jtag: entity work.sim_jtag;