core_dummy.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7 use work.wishbone_types.all;
   8
   9 entity core is
  10     generic (
  11         SIM : boolean := false;
  12         DISABLE_FLATTEN : boolean := false;
  13         EX1_BYPASS : boolean := true;
  14         HAS_FPU : boolean := true;
  15         HAS_BTC : boolean := true;
  16         RESET_ADDRESS : std_ulogic_vector(63 downto 0) := (others => '0');
  17         ALT_RESET_ADDRESS : std_ulogic_vector(63 downto 0) := (others => '0');
  18         LOG_LENGTH : natural := 512
  19         );
  20     port (
  21         clk          : in std_ulogic;
  22         rst          : in std_ulogic;
  23
  24         -- Alternate reset (0xffff0000) for use by DRAM init fw
  25         alt_reset    : in std_ulogic;
  26
  27         -- Wishbone interface
  28         wishbone_insn_in  : in wishbone_slave_out;
  29         wishbone_insn_out : out wishbone_master_out;
  30
  31         wishbone_data_in  : in wishbone_slave_out;
  32         wishbone_data_out : out wishbone_master_out;
  33
  34         dmi_addr        : in std_ulogic_vector(3 downto 0);
  35         dmi_din         : in std_ulogic_vector(63 downto 0);
  36         dmi_dout        : out std_ulogic_vector(63 downto 0);
  37         dmi_req         : in std_ulogic;
  38         dmi_wr          : in std_ulogic;
  39         dmi_ack         : out std_ulogic;
  40
  41         ext_irq         : in std_ulogic;
  42
  43         terminated_out   : out std_logic;
  44
  45     -- for verilator debugging
  46     nia_req: out std_ulogic;
  47     nia: out std_ulogic_vector(63 downto 0);
  48     msr_o: out std_ulogic_vector(63 downto 0);
  49     insn: out std_ulogic_vector(31 downto 0);
  50         ldst_req: out std_ulogic;
  51         ldst_addr: out std_ulogic_vector(63 downto 0)
  52         );
  53 end core;
  54
  55 architecture behave of core is
  56 begin
  57
  58 end behave;