2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
7 use work.wishbone_types.all;
12 architecture behave of core_tb is
13 signal clk, rst: std_logic;
16 constant clk_period : time := 10 ns;
22 MEMORY_SIZE => 524288,
23 RAM_INIT_FILE => "simple_ram_behavioural.bin",
36 wait for clk_period/2;
38 wait for clk_period/2;
44 wait for 10*clk_period;
49 jtag: entity work.sim_jtag;