core_tb.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7 use work.wishbone_types.all;
   8
   9 entity core_tb is
  10 end core_tb;
  11
  12 architecture behave of core_tb is
  13         signal clk, rst: std_logic;
  14
  15         -- testbench signals
  16         constant clk_period : time := 10 ns;
  17
  18         -- Dummy DRAM
  19         signal wb_dram_in : wishbone_master_out;
  20         signal wb_dram_out : wishbone_slave_out;
  21         signal wb_dram_ctrl_in : wb_io_master_out;
  22         signal wb_dram_ctrl_out : wb_io_slave_out;
  23 begin
  24
  25     soc0: entity work.soc
  26         generic map(
  27             SIM => true,
  28             MEMORY_SIZE => (384*1024),
  29             RAM_INIT_FILE => "main_ram.bin",
  30             RESET_LOW => false,
  31             CLK_FREQ => 100000000
  32             )
  33         port map(
  34             rst => rst,
  35             system_clk => clk,
  36             uart0_rxd => '0',
  37             uart0_txd => open,
  38             wb_dram_in => wb_dram_in,
  39             wb_dram_out => wb_dram_out,
  40             wb_dram_ctrl_in => wb_dram_ctrl_in,
  41             wb_dram_ctrl_out => wb_dram_ctrl_out,
  42             alt_reset => '0'
  43             );
  44
  45     clk_process: process
  46     begin
  47         clk <= '0';
  48         wait for clk_period/2;
  49         clk <= '1';
  50         wait for clk_period/2;
  51     end process;
  52
  53     rst_process: process
  54     begin
  55         rst <= '1';
  56         wait for 10*clk_period;
  57         rst <= '0';
  58         wait;
  59     end process;
  60
  61     jtag: entity work.sim_jtag;
  62
  63     -- Dummy DRAM
  64     wb_dram_out.ack <= wb_dram_in.cyc and wb_dram_in.stb;
  65     wb_dram_out.dat <= x"FFFFFFFFFFFFFFFF";
  66     wb_dram_out.stall <= '0';
  67     wb_dram_ctrl_out.ack <= wb_dram_ctrl_in.cyc and wb_dram_ctrl_in.stb;
  68     wb_dram_ctrl_out.dat <= x"FFFFFFFF";
  69     wb_dram_ctrl_out.stall <= '0';
  70
  71 end;