core_tb.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4 use std.textio.all;
   5
   6 library work;
   7 use work.common.all;
   8 use work.wishbone_types.all;
   9
  10 entity core_tb is
  11 end core_tb;
  12
  13 architecture behave of core_tb is
  14         signal clk, rst: std_logic;
  15
  16         -- testbench signals
  17         constant clk_period : time := 10 ns;
  18 begin
  19
  20     soc0: entity work.soc
  21         generic map(
  22             SIM => true,
  23             MEMORY_SIZE => 524288,
  24             RAM_INIT_FILE => "simple_ram_behavioural.bin",
  25             RESET_LOW => false
  26             )
  27         port map(
  28             rst => rst,
  29             system_clk => clk,
  30             uart0_rxd => '0',
  31             uart0_txd => open
  32             );
  33
  34         clk_process: process
  35         begin
  36                 clk <= '0';
  37                 wait for clk_period/2;
  38                 clk <= '1';
  39                 wait for clk_period/2;
  40         end process;
  41
  42         rst_process: process
  43         begin
  44                 rst <= '1';
  45                 wait for 10*clk_period;
  46                 rst <= '0';
  47                 wait;
  48         end process;
  49 end;