2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
7 use work.wishbone_types.all;
12 architecture behave of core_tb is
13 signal clk, rst: std_logic;
16 constant clk_period : time := 10 ns;
19 signal wb_dram_in : wishbone_master_out;
20 signal wb_dram_out : wishbone_slave_out;
21 signal wb_dram_ctrl_in : wb_io_master_out;
22 signal wb_dram_ctrl_out : wb_io_slave_out;
28 MEMORY_SIZE => (384*1024),
29 RAM_INIT_FILE => "main_ram.bin",
38 wb_dram_in => wb_dram_in,
39 wb_dram_out => wb_dram_out,
40 wb_dram_ctrl_in => wb_dram_ctrl_in,
41 wb_dram_ctrl_out => wb_dram_ctrl_out,
48 wait for clk_period/2;
50 wait for clk_period/2;
56 wait for 10*clk_period;
61 jtag: entity work.sim_jtag;
64 wb_dram_out.ack <= wb_dram_in.cyc and wb_dram_in.stb;
65 wb_dram_out.dat <= x"FFFFFFFFFFFFFFFF";
66 wb_dram_out.stall <= '0';
67 wb_dram_ctrl_out.ack <= wb_dram_ctrl_in.cyc and wb_dram_ctrl_in.stb;
68 wb_dram_ctrl_out.dat <= x"FFFFFFFF";
69 wb_dram_ctrl_out.stall <= '0';