2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
7 use work.glibc_random.all;
12 architecture behave of countzero_tb is
13 constant clk_period: time := 10 ns;
14 signal rs: std_ulogic_vector(63 downto 0);
15 signal is_32bit, count_right: std_ulogic := '0';
16 signal result: std_ulogic_vector(63 downto 0);
17 signal randno: std_ulogic_vector(63 downto 0);
18 signal clk: std_ulogic;
21 zerocounter_0: entity work.zero_counter
26 count_right => count_right,
33 wait for clk_period/2;
35 wait for clk_period/2;
39 variable r: std_ulogic_vector(63 downto 0);
41 -- test with input = 0
42 report "test zero input";
43 rs <= (others => '0');
47 assert result = x"0000000000000040"
48 report "bad cntlzd 0 = " & to_hstring(result);
51 assert result = x"0000000000000040"
52 report "bad cnttzd 0 = " & to_hstring(result);
56 assert result = x"0000000000000020"
57 report "bad cntlzw 0 = " & to_hstring(result);
60 assert result = x"0000000000000020"
61 report "bad cnttzw 0 = " & to_hstring(result);
63 report "test cntlzd/w";
65 for j in 0 to 100 loop
72 assert to_integer(unsigned(result)) = i
73 report "bad cntlzd " & to_hstring(rs) & " -> " & to_hstring(result);
74 rs <= r(31 downto 0) & r(63 downto 32);
78 assert to_integer(unsigned(result)) = i
79 report "bad cntlzw " & to_hstring(rs) & " -> " & to_hstring(result);
81 assert to_integer(unsigned(result)) = 32
82 report "bad cntlzw " & to_hstring(rs) & " -> " & to_hstring(result);
84 r := '0' & r(63 downto 1);
88 report "test cnttzd/w";
90 for j in 0 to 100 loop
97 assert to_integer(unsigned(result)) = i
98 report "bad cnttzd " & to_hstring(rs) & " -> " & to_hstring(result);
102 assert to_integer(unsigned(result)) = i
103 report "bad cnttzw " & to_hstring(rs) & " -> " & to_hstring(result);
105 assert to_integer(unsigned(result)) = 32
106 report "bad cnttzw " & to_hstring(rs) & " -> " & to_hstring(result);
108 r := r(62 downto 0) & '0';