1 2020-09-18 David Faust <david.faust@oracle.com>
3 * bpf.cpu (insn-op-code-alu): Add SDIV and SMOD.
4 (define-alu-insn-bin, daib): Take ISAs as an argument.
5 (define-alu-instructions): Update calls to daib pmacro with
6 ISAs; add sdiv and smod.
8 2020-09-08 David Faust <david.faust@oracle.com>
10 * bpf.cpu (define-alu-instructions): Correct semantic operators
11 for div, mod to unsigned versions.
13 2020-09-01 Alan Modra <amodra@gmail.com>
15 * mep-core.cpu (f-8s8a2, f-12s4a2, f-17s16a2): Multiply signed
16 value by two rather than shifting left.
17 (f-24s5a2n): Similarly multiply signed f-24s5a2n-hi to extract.
19 2020-08-26 David Faust <david.faust@oracle.com>
21 * bpf.cpu (arch bpf): Add xbpf mach and isas.
22 (define-xbpf-isa) New pmacro.
23 (all-isas) Add xbpfle,xbpfbe.
24 (endian-isas): New pmacro.
26 (model xbpf-def): Likewise.
27 (h-gpr): Add xbpf mach.
28 (f-dstle, f-srcle, dstle, srcle): Add xbpfle isa.
29 (f-dstbe, f-srcbe, dstbe, srcbe): Add xbpfbe isa.
30 (define-alu-insn-un): Use new endian-isas pmacro.
31 (define-alu-insn-bin, define-alu-insn-mov): Likewise.
32 (define-endian-insn, define-lddw): Likewise.
33 (dlind, dxli, dxsi, dsti): Likewise.
34 (define-cond-jump-insn, define-call-insn): Likewise.
35 (define-atomic-insns): Likewise.
37 2020-07-04 Nick Clifton <nickc@redhat.com>
39 Binutils 2.35 branch created.
41 2020-06-25 David Faust <david.faust@oracle.com>
43 * bpf.cpu (f-offset16): Change type from INT to HI.
44 (dxli): Simplify memory access.
46 (define-endian-insn): Update c-call in semantics.
50 2020-06-02 Jose E. Marchesi <jose.marchesi@oracle.com>
52 * bpf.cpu (define-bpf-isa): Set base-insn-bitsize to 64.
53 * bpf.opc (bpf_print_insn): Do not set endian_code here.
55 2020-06-02 Jose E. Marchesi <jose.marchesi@oracle.com>
57 * mep.opc (print_slot_insn): Pass the insn endianness to
60 2020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
61 David Faust <david.faust@oracle.com>
63 * bpf.cpu (define-alu-insn-un): Add definitions of semantics.
64 (define-alu-insn-mov): Likewise.
66 (define-alu-instructions): Likewise.
67 (define-endian-insn): Likewise.
68 (define-lddw): Likewise.
74 (define-ldstx-insns): Likewise.
75 (define-st-insns): Likewise.
76 (define-cond-jump-insn): Likewise.
78 (define-condjump-insns): Likewise.
79 (define-call-insn): Likewise.
82 (define-atomic-insns): Likewise.
83 (sem-exchange-and-add): New macro.
84 * bpf.cpu ("brkpt"): New instruction.
85 (bpfbf): Set word-bitsize to 32 and insn-endian big.
86 (h-gpr): Prefer r0 to `a' and r6 to `ctx'.
87 (h-pc): Expand definition.
88 * bpf.opc (bpf_print_insn): Set endian_code to BIG.
90 2020-05-21 Alan Modra <amodra@gmail.com>
92 * mep.opc (mep_cgen_expand_macros_and_parse_operand): Replace
93 "if (x) free (x)" with "free (x)".
95 2020-05-19 Stafford Horne <shorne@gmail.com>
98 * or1k.cpu (arch or1k): Remove or64 and or64nd machs.
99 (ORBIS-MACHS, ORFPX32-MACHS): Remove pmacros.
100 (cpu or1k64bf, mach or64, mach or64nd): Remove definitions.
101 * or1kcommon.cpu (h-fdr): Remove hardware.
102 * or1korfpx.cpu (rDDF, rADF, rBDF): Remove operand definitions.
103 (float-regreg-insn): Remove lf- mnemonic -d instruction pattern.
104 (float-setflag-insn-base): Remove lf-sf mnemonic -d pattern.
105 (float-cust-insn): Remove "lf-cust" cust-num "-d" pattern.
106 (lf-rem-d, lf-itof-d, lf-ftoi-d, lf-madd-d): Remove.
108 2020-02-16 David Faust <david.faust@oracle.com>
110 * bpf.cpu (define-cond-jump-insn): Renamed from djci.
111 (dcji) New version with support for JMP32
113 2020-02-03 Alan Modra <amodra@gmail.com>
115 * m32c.cpu (f-dsp-64-s16): Mask before shifting signed value.
117 2020-02-01 Alan Modra <amodra@gmail.com>
119 * frv.cpu (f-u12): Multiply rather than left shift signed values.
120 (f-label16, f-label24): Likewise.
122 2020-01-30 Alan Modra <amodra@gmail.com>
124 * m32c.cpu (f-src32-rn-unprefixed-QI): Shift before inverting.
125 (f-src32-rn-prefixed-QI, f-dst32-rn-unprefixed-QI): Likewise.
126 (f-dst32-rn-prefixed-QI): Likewise.
127 (f-dsp-32-s32): Mask before shifting left.
128 (f-dsp-48-u32, f-dsp-48-s32): Likewise.
129 (f-bitbase32-16-s11-unprefixed): Multiply signed field rather than
131 (f-bitbase32-24-s11-prefixed, f-bitbase32-24-s19-prefixed): Likewise.
132 (h-gr-SI): Mask before shifting.
134 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
136 * bpf.cpu (define-alu-insn-un): The unary BPF instructions
137 (neg and neg32) use OP_SRC_K even if they operate only in
140 2020-01-18 Nick Clifton <nickc@redhat.com>
142 Binutils 2.34 branch created.
144 2020-01-13 Alan Modra <amodra@gmail.com>
146 * fr30.cpu (f-disp9, f-disp10, f-s10, f-rel9, f-rel12): Don't
147 left shift signed values.
149 2020-01-06 Alan Modra <amodra@gmail.com>
151 * m32c.cpu (f-dsp-8-u16, f-dsp-8-s16): Rearrange to mask any sign
152 bits before shifting rather than masking after shifting.
153 (f-dsp-16-u16, f-dsp-16-s16, f-dsp-32-u16, f-dsp-32-s16): Likewise.
154 (f-dsp-40-u16, f-dsp-40-s16, f-dsp-48-u16, f-dsp-48-s16): Likewise.
155 (f-dsp-64-u16, f-dsp-8-s24): Likewise.
156 (f-bitbase32-16-s19-unprefixed): Avoid signed left shift.
158 2020-01-04 Alan Modra <amodra@gmail.com>
160 * m32r.cpu (f-disp8): Avoid left shift of negative values.
161 (f-disp16, f-disp24): Likewise.
163 2019-12-23 Alan Modra <amodra@gmail.com>
165 * iq2000.cpu (f-offset): Avoid left shift of negative values.
167 2019-12-20 Alan Modra <amodra@gmail.com>
169 * or1korbis.cpu (f-disp26, f-disp21): Don't left shift negative values.
171 2019-12-17 Alan Modra <amodra@gmail.com>
173 * bpf.cpu (f-imm64): Avoid signed overflow.
175 2019-12-16 Alan Modra <amodra@gmail.com>
177 * xstormy16.cpu (f-rel12a): Avoid signed overflow.
179 2019-12-11 Alan Modra <amodra@gmail.com>
181 * epiphany.cpu (f-sdisp11): Don't sign extend with shifts.
182 * lm32.cpu (f-branch, f-vall): Likewise.
183 * m32.cpu (f-lab-8-16): Likewise.
185 2019-12-11 Alan Modra <amodra@gmail.com>
187 * epiphany.cpu (f-simm8, f-simm24): Use multiply rather than
188 shift left to avoid UB on left shift of negative values.
190 2019-11-20 Jose E. Marchesi <jose.marchesi@oracle.com>
192 * bpf.cpu: Fix comment describing the 128-bit instruction format.
194 2019-09-09 Phil Blundell <pb@pbcl.net>
196 binutils 2.33 branch created.
198 2019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
200 * bpf.cpu (h-gpr): when disassembling, use %r0 and %r6 instead of
203 2019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
205 * bpf.cpu (dlabs): New pmacro.
208 2019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
210 * bpf.cpu (dlsi): ldabs and ldind instructions do not take an
211 explicit 'dst' argument.
213 2019-06-13 Stafford Horne <shorne@gmail.com>
215 * or1korfpx.cpu (float-setflag-insn-base): Add 'sf' to symbol.
217 2019-06-13 Stafford Horne <shorne@gmail.com>
219 * or1k.cpu (or64nd, or32nd, or1200nd): Update comment.a
220 (l-adrp): Improve comment.
222 2019-06-13 Stafford Horne <shorne@gmail.com>
224 * or1korfpx.cpu (insn-opcode-float-regreg): Add SFUEQ_S, SFUNE_S,
225 SFUGT_S, SFUGE_S, SFULT_S, SFULE_S, SFUN_S, SFUEQ_D, SFUNE_D, SFUGT_D,
226 SFUGE_D, SFULT_D, SFULE_D, SFUN_D opcodes.
227 (float-setflag-insn-base): New pmacro based on float-setflag-insn.
228 (float-setflag-symantics, float-setflag-unordered-cmp-symantics,
229 float-setflag-unordered-symantics): New pmacro for instruction
231 (float-setflag-insn): Update to use float-setflag-insn-base.
232 (float-setflag-unordered-insn): New pmacro for generating instructions.
234 2019-06-13 Andrey Bacherov <avbacherov@opencores.org>
235 Stafford Horne <shorne@gmail.com>
237 * or1k.cpu (ORFPX64A32-MACHS): New pmacro.
238 (ORFPX-MACHS): Removed pmacro.
239 * or1k.opc (or1k_cgen_insn_supported): New function.
240 (CGEN_VALIDATE_INSN_SUPPORTED): Define macro.
241 (parse_regpair, print_regpair): New functions.
242 * or1kcommon.cpu (h-spr, spr-shift, spr-address, h-gpr): Reorder
244 (h-fdr): Update comment to indicate or64.
245 (reg-pair-reg-lo, reg-pair-reg-hi): New pmacros for register pairs.
246 (h-fd32r): New hardware for 64-bit fpu registers.
247 (h-i64r): New hardware for 64-bit int registers.
248 * or1korbis.cpu (f-resv-8-1): New field.
249 * or1korfpx.cpu (rDSF, rASF, rBSF): Update attribute to ORFPX32-MACHS.
250 (rDDF, rADF, rBDF): Update operand comment to indicate or64.
251 (f-rdoff-10-1, f-raoff-9-1, f-rboff-8-1): New fields.
252 (h-roff1): New hardware.
253 (double-field-and-ops mnemonic): New pmacro to generate operations
254 rDD32F, rAD32F, rBD32F, rDDI and rADI.
255 (float-regreg-insn): Update single precision generator to MACH
256 ORFPX32-MACHS. Add generator for or32 64-bit instructions.
257 (float-setflag-insn): Update single precision generator to MACH
258 ORFPX32-MACHS. Fix double instructions from single to double
259 precision. Add generator for or32 64-bit instructions.
260 (float-cust-insn cust-num): Update single precision generator to MACH
261 ORFPX32-MACHS. Add generator for or32 64-bit instructions.
262 (lf-rem-s, lf-itof-s, lf-ftoi-s, lf-madd-s): Update MACH to
264 (lf-rem-d): Fix operation from mod to rem.
265 (lf-rem-d32, lf-itof-d32, lf-ftoi-d32, lf-madd-d32): New instruction.
266 (lf-itof-d): Fix operands from single to double.
267 (lf-ftoi-d): Update operand mode from DI to WI.
269 2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
274 2018-06-24 Nick Clifton <nickc@redhat.com>
278 2018-10-05 Richard Henderson <rth@twiddle.net>
279 Stafford Horne <shorne@gmail.com>
281 * or1korbis.cpu (insn-opcode-mac): Add opcodes for MACU and MSBU.
282 (insn-opcode-alu-regreg): Add opcodes for MULD and MULDU.
283 (l-mul): Fix overflow support and indentation.
284 (l-mulu): Fix overflow support and indentation.
285 (l-muld, l-muldu, l-msbu, l-macu): New instructions.
286 (l-div); Remove incorrect carry behavior.
287 (l-divu): Fix carry and overflow behavior.
288 (l-mac): Add overflow support.
289 (l-msb, l-msbu): Add carry and overflow support.
291 2018-10-05 Richard Henderson <rth@twiddle.net>
293 * or1k.opc (parse_disp26): Add support for plta() relocations.
294 (parse_disp21): New function.
295 (or1k_rclass): New enum.
296 (or1k_rtype): New enum.
297 (or1k_imm16_relocs): Define new PO and SPO relocation mappings.
298 (parse_reloc): Add new po(), gotpo() and gottppo() for LO13 relocations.
299 (parse_imm16): Add support for the new 21bit and 13bit relocations.
300 * or1korbis.cpu (f-disp26): Don't assume SI.
301 (f-disp21): New pc-relative 21-bit 13 shifted to right.
302 (insn-opcode): Add ADRP.
303 (l-adrp): New instruction.
305 2018-10-05 Richard Henderson <rth@twiddle.net>
307 * or1k.opc: Add RTYPE_ enum.
308 (INVALID_STORE_RELOC): New string.
309 (or1k_imm16_relocs): New array array.
310 (parse_reloc): New static function that just does the parsing.
311 (parse_imm16): New static function for generic parsing.
312 (parse_simm16): Change to just call parse_imm16.
313 (parse_simm16_split): New function.
314 (parse_uimm16): Change to call parse_imm16.
315 (parse_uimm16_split): New function.
316 * or1korbis.cpu (simm16-split): Change to use new simm16_split.
317 (uimm16-split): Change to use new uimm16_split.
319 2018-07-24 Alan Modra <amodra@gmail.com>
322 * or1kcommon.cpu (spr-reg-indices): Fix description typo.
324 2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
326 * or1kcommon.cpu (spr-reg-info): Typo fix.
328 2018-03-03 Alan Modra <amodra@gmail.com>
330 * frv.opc: Include opintl.h.
331 (add_next_to_vliw): Use opcodes_error_handler to print error.
332 Standardize error message.
333 (fr500_check_insn_major_constraints, frv_vliw_add_insn): Likewise.
335 2018-01-13 Nick Clifton <nickc@redhat.com>
339 2017-03-15 Stafford Horne <shorne@gmail.com>
341 * or1kcommon.cpu: Add pc set semantics to also update ppc.
343 2016-10-06 Alan Modra <amodra@gmail.com>
345 * mep.opc (expand_string): Add fall through comment.
347 2016-03-03 Alan Modra <amodra@gmail.com>
349 * fr30.cpu (f-m4): Replace bogus comment with a better guess
350 at what is really going on.
352 2016-03-02 Alan Modra <amodra@gmail.com>
354 * fr30.cpu (f-m4): Replace -1 << 4 with -16.
356 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
358 * epiphany.opc (epiphany_print_insn): Set info->bytes_per_line to
359 a constant to better align disassembler output.
361 2014-07-20 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
363 * or1korbis.cpu (l-msync, l-psync, l-csync): New instructions.
365 2014-06-12 Alan Modra <amodra@gmail.com>
367 * or1k.opc: Whitespace fixes.
369 2014-05-08 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
371 * or1korbis.cpu (h-atomic-reserve): New hardware.
372 (h-atomic-address): Likewise.
373 (insn-opcode): Add opcodes for LWA and SWA.
374 (atomic-reserve): New operand.
375 (atomic-address): Likewise.
376 (l-lwa, l-swa): New instructions.
377 (l-lbs): Fix typo in comment.
378 (store-insn): Clear atomic reserve on store to atomic-address.
379 Fix register names in fmt field.
381 2014-04-22 Christian Svensson <blue@cmd.nu>
383 * openrisc.cpu: Delete.
384 * openrisc.opc: Delete.
385 * or1k.cpu: New file.
386 * or1k.opc: New file.
387 * or1kcommon.cpu: New file.
388 * or1korbis.cpu: New file.
389 * or1korfpx.cpu: New file.
391 2013-12-07 Mike Frysinger <vapier@gentoo.org>
393 * epiphany.opc: Remove +x file mode.
395 2013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
398 * lm32.cpu (Control and status registers): Add CFG2, PSW,
399 TLBVADDR, TLBPADDR and TLBBADVADDR.
401 2012-11-30 Oleg Raikhman <oleg@adapteva.com>
402 Joern Rennecke <joern.rennecke@embecosm.com>
404 * epiphany.cpu (keyword gr-names): Move sb/sl/ip after r9/r10/r12.
405 (load_insn): Add NO-DIS attribute to x, p, d, dpm, dl0, dl0.l.
406 (testset-insn): Add NO_DIS attribute to t.l.
407 (store-insn): Add NO-DIS attribute to x.l, p.l, d.l, dpm.l, dl0.l.
408 (move-insns): Add NO-DIS attribute to cmov.l.
409 (op-mmr-movts): Add NO-DIS attribute to movts.l.
410 (op-mmr-movfs): Add NO-DIS attribute to movfs.l.
411 (op-rrr): Add NO-DIS attribute to .l.
412 (shift-rrr): Add NO-DIS attribute to .l.
413 (op-shift-rri): Add NO-DIS attribute to i32.l.
414 (bitrl, movtl): Add NO-DIS attribute.
415 (op-iextrrr): Add NO-DIS attribute to .l
416 (op-two_operands-float, op-fabs-float): Add NO-DIS attribute to f32.l.
417 (op-fix2float-float, op-float2fix-float, op-fextop-float): Likewise.
419 2012-02-27 Alan Modra <amodra@gmail.com>
421 * mt.opc (print_dollarhex): Trim values to 32 bits.
423 2011-12-15 Nick Clifton <nickc@redhat.com>
425 * frv.opc (parse_uhi16): Fix handling of %hi operator on 64-bit
428 2011-10-26 Joern Rennecke <joern.rennecke@embecosm.com>
430 * epiphany.opc (parse_branch_addr): Fix type of valuep.
431 Cast value before printing it as a long.
432 (parse_postindex): Fix type of valuep.
434 2011-10-25 Joern Rennecke <joern.rennecke@embecosm.com>
436 * cpu/epiphany.cpu: New file.
437 * cpu/epiphany.opc: New file.
439 2011-08-22 Nick Clifton <nickc@redhat.com>
441 * fr30.cpu: Newly contributed file.
442 * fr30.opc: Likewise.
443 * ip2k.cpu: Likewise.
444 * ip2k.opc: Likewise.
445 * mep-avc.cpu: Likewise.
446 * mep-avc2.cpu: Likewise.
447 * mep-c5.cpu: Likewise.
448 * mep-core.cpu: Likewise.
449 * mep-default.cpu: Likewise.
450 * mep-ext-cop.cpu: Likewise.
451 * mep-fmax.cpu: Likewise.
452 * mep-h1.cpu: Likewise.
453 * mep-ivc2.cpu: Likewise.
454 * mep-rhcop.cpu: Likewise.
455 * mep-sample-ucidsp.cpu: Likewise.
458 * openrisc.cpu: Likewise.
459 * openrisc.opc: Likewise.
460 * xstormy16.cpu: Likewise.
461 * xstormy16.opc: Likewise.
463 2010-10-08 Pierre Muller <muller@ics.u-strasbg.fr>
465 * frv.opc: #undef DEBUG.
467 2010-07-03 DJ Delorie <dj@delorie.com>
469 * m32c.cpu (f-dsp-8-s24): Mask high byte after shifting it.
471 2010-02-11 Doug Evans <dje@sebabeach.org>
473 * m32r.cpu (HASH-PREFIX): Delete.
474 (duhpo, dshpo): New pmacros.
475 (simm8, simm16): Delete HASH-PREFIX attribute, define with dshpo.
476 (uimm3, uimm4, uimm5, uimm8, uimm16, imm1): Delete HASH-PREFIX
477 attribute, define with dshpo.
478 (uimm24): Delete HASH-PREFIX attribute.
479 * m32r.opc (CGEN_PRINT_NORMAL): Delete.
480 (print_signed_with_hash_prefix): New function.
481 (print_unsigned_with_hash_prefix): New function.
482 * xc16x.cpu (dowh): New pmacro.
483 (upof16): Define with dowh, specify print handler.
484 (qbit, qlobit, qhibit): Ditto.
486 * xc16x.opc (CGEN_PRINT_NORMAL): Delete.
487 (print_with_dot_prefix): New functions.
488 (print_with_pof_prefix, print_with_pag_prefix): New functions.
490 2010-01-24 Doug Evans <dje@sebabeach.org>
492 * frv.cpu (floating-point-conversion): Update call to fp conv op.
493 (floating-point-dual-conversion, ne-floating-point-dual-conversion,
494 conditional-floating-point-conversion, ne-floating-point-conversion,
495 float-parallel-mul-add-double-semantics): Ditto.
497 2010-01-05 Doug Evans <dje@sebabeach.org>
499 * m32c.cpu (f-dsp-32-u24): Fix mode of extract handler.
500 (f-dsp-40-u20, f-dsp-40-u24): Ditto.
502 2010-01-02 Doug Evans <dje@sebabeach.org>
504 * m32c.opc (parse_signed16): Fix typo.
506 2009-12-11 Nick Clifton <nickc@redhat.com>
508 * frv.opc: Fix shadowed variable warnings.
509 * m32c.opc: Fix shadowed variable warnings.
511 2009-11-14 Doug Evans <dje@sebabeach.org>
513 Must use VOID expression in VOID context.
514 * xc16x.cpu (mov4): Fix mode of `sequence'.
515 (mov9, mov10): Ditto.
516 (movbsrr, moveb1, jmprel, jmpseg, jmps): Fix mode of `if'.
517 (callr, callseg, calls, trap, rets, reti): Ditto.
518 (jb, jbc, jnb, jnbs): Fix mode of `if'. Comment out no-op `sll'.
519 (atomic, extr, extp, extp1, extpg1, extpr, extpr1): Fix mode of `cond'.
520 (exts, exts1, extsr, extsr1, prior): Ditto.
522 2009-10-23 Doug Evans <dje@sebabeach.org>
524 * m32c.opc (opc.h): cgen-types.h -> cgen/basic-modes.h.
525 cgen-ops.h -> cgen/basic-ops.h.
527 2009-09-25 Alan Modra <amodra@bigpond.net.au>
529 * m32r.cpu (stb-plus): Typo fix.
531 2009-09-23 Doug Evans <dje@sebabeach.org>
533 * m32r.cpu (sth-plus): Fix address mode and calculation.
535 (clrpsw): Fix mask calculation.
536 (bset, bclr, btst): Make mode in bit calculation match expression.
538 * xc16x.cpu (rtl-version): Set to 0.8.
539 (gr-names, ext-names,psw-names): Update, print-name -> enum-prefix,
540 make uppercase. Remove unnecessary name-prefix spec.
541 (grb-names, conditioncode-names, extconditioncode-names): Ditto.
542 (grb8-names, r8-names, regmem8-names, regdiv8-names): Ditto.
543 (reg0-name, reg0-name1, regbmem8-names, memgr8-names): Ditto.
544 (h-cr): New hardware.
545 (muls): Comment out parts that won't compile, add fixme.
546 (mulu, divl, divlu, jmpabs, jmpa-, jmprel, jbc, jnbs, callr): Ditto.
547 (scxti, scxtmg, scxtm, bclear, bclr18, bset19, bitset, bmov): Ditto.
548 (bmovn, band, bor, bxor, bcmp, bfldl, bfldh): Ditto.
550 2009-07-16 Doug Evans <dje@sebabeach.org>
552 * cpu/simplify.inc (*): One line doc strings don't need \n.
553 (df): Invoke define-full-ifield instead of claiming it's an alias.
555 (dnop): Mark as deprecated.
557 2009-06-22 Alan Modra <amodra@bigpond.net.au>
559 * m32c.opc (parse_lab_5_3): Use correct enum.
561 2009-01-07 Hans-Peter Nilsson <hp@axis.com>
563 * frv.cpu (mabshs): Explicitly sign-extend arguments of abs to DI.
564 (DI-ext-HI, DI-ext-UHI, DI-ext-DI): New pmacros.
565 (media-arith-sat-semantics): Explicitly sign- or zero-extend
566 arguments of "operation" to DI using "mode" and the new pmacros.
568 2009-01-03 Hans-Peter Nilsson <hp@axis.com>
570 * cris.cpu (cris-implemented-writable-specregs-v32): Correct size
573 2008-12-23 Jon Beniston <jon@beniston.com>
575 * lm32.cpu: New file.
576 * lm32.opc: New file.
578 2008-01-29 Alan Modra <amodra@bigpond.net.au>
580 * mt.opc (parse_imm16): Apply 2007-09-26 opcodes/mt-asm.c change
583 2007-10-22 Hans-Peter Nilsson <hp@axis.com>
585 * cris.cpu (movs, movu): Use result of extension operation when
588 2007-07-04 Nick Clifton <nickc@redhat.com>
590 * cris.cpu: Update copyright notice to refer to GPLv3.
591 * frv.cpu, frv.opc, iq10.cpu, iq2000m.cpu, iq2000.opc, m32c.cpu,
592 m32c.opc, m32r.cpu, m32r.opc, mt.cpu, mt.opc, sh64-compact.cpu,
593 sh64-media.cpu, sh.cpu, sh.opc, simplify.inc, xc16x.cpu,
595 * iq2000.cpu: Fix copyright notice to refer to FSF.
597 2007-04-30 Mark Salter <msalter@sadr.localdomain>
599 * frv.cpu (spr-names): Support new coprocessor SPR registers.
601 2007-04-20 Nick Clifton <nickc@redhat.com>
603 * xc16x.cpu: Restore after accidentally overwriting this file with
606 2007-03-29 DJ Delorie <dj@redhat.com>
608 * m32c.cpu (Imm-8-s4n): Fix print hook.
609 (Lab-24-8, Lab-32-8, Lab-40-8): Fix.
610 (arith-jnz-imm4-dst-defn): Make relaxable.
611 (arith-jnz16-imm4-dst-defn): Fix encodings.
613 2007-03-20 DJ Delorie <dj@redhat.com>
615 * m32c.cpu (f-dsp-40-u20, f-dsp-48-u20, Dsp-40-u20, Dsp-40-u20,
617 (src16-16-20-An-relative-*): New.
618 (dst16-*-20-An-relative-*): New.
619 (dst16-16-16sa-*): New
620 (dst16-16-16ar-*): New
621 (dst32-16-16sa-Unprefixed-*): New
622 (jsri): Fix operands.
623 (setzx): Fix encoding.
625 2007-03-08 Alan Modra <amodra@bigpond.net.au>
627 * m32r.opc: Formatting.
629 2006-05-22 Nick Clifton <nickc@redhat.com>
631 * iq2000.cpu: Fix include paths for iq2000m.cpu and iq10.cpu.
633 2006-04-10 DJ Delorie <dj@redhat.com>
635 * m32c.opc (parse_unsigned_bitbase): Take a new parameter which
636 decides if this function accepts symbolic constants or not.
637 (parse_signed_bitbase): Likewise.
638 (parse_unsigned_bitbase8): Pass the new parameter.
639 (parse_unsigned_bitbase11): Likewise.
640 (parse_unsigned_bitbase16): Likewise.
641 (parse_unsigned_bitbase19): Likewise.
642 (parse_unsigned_bitbase27): Likewise.
643 (parse_signed_bitbase8): Likewise.
644 (parse_signed_bitbase11): Likewise.
645 (parse_signed_bitbase19): Likewise.
647 2006-03-13 DJ Delorie <dj@redhat.com>
649 * m32c.cpu (Bit3-S): New.
651 * m32c.opc (parse_bit3_S): New.
653 * m32c.cpu (decimal-subtraction16-insn): Add second operand.
654 (btst): Add optional :G suffix for MACH32.
656 (pop.w:G): Add optional :G suffix for MACH16.
657 (push.b.imm): Fix syntax.
659 2006-03-10 DJ Delorie <dj@redhat.com>
661 * m32c.cpu (mul.l): New.
664 2006-03-03 Shrirang Khisti <shrirangk@kpitcummins.com)
666 * xc16x.opc (parse_hash): Return NULL if the input was parsed or
667 an error message otherwise.
668 (parse_dot, parse_pof, parse_pag, parse_sof, parse_seg): Likewise.
669 Fix up comments to correctly describe the functions.
671 2006-02-24 DJ Delorie <dj@redhat.com>
673 * m32c.cpu (RL_TYPE): New attribute, with macros.
674 (Lab-8-24): Add RELAX.
675 (unary-insn-defn-g, binary-arith-imm-dst-defn,
676 binary-arith-imm4-dst-defn): Add 1ADDR attribute.
677 (binary-arith-src-dst-defn): Add 2ADDR attribute.
678 (jcnd16-5, jcnd16, jcnd32, jmp16.s, jmp16.b, jmp16.w, jmp16.a,
679 jmp32.s, jmp32.b, jmp32.w, jmp32.a, jsr16.w, jsr16.a): Add JUMP
681 (jsri16, jsri32): Add 1ADDR attribute.
682 (jsr32.w, jsr32.a): Add JUMP attribute.
684 2006-02-17 Shrirang Khisti <shrirangk@kpitcummins.com>
685 Anil Paranjape <anilp1@kpitcummins.com>
686 Shilin Shakti <shilins@kpitcummins.com>
688 * xc16x.cpu: New file containing complete CGEN specific XC16X CPU
690 * xc16x.opc: New file containing supporting XC16C routines.
692 2006-02-10 Nick Clifton <nickc@redhat.com>
694 * iq2000.opc (parse_hi16): Truncate shifted values to 16 bits.
696 2006-01-06 DJ Delorie <dj@redhat.com>
698 * m32c.cpu (mov.w:q): Fix mode.
699 (push32.b.imm): Likewise, for the comment.
701 2005-12-16 Nathan Sidwell <nathan@codesourcery.com>
703 Second part of ms1 to mt renaming.
704 * mt.cpu (define-arch, define-isa): Set name to mt.
705 (define-mach): Adjust.
706 * mt.opc (CGEN_ASM_HASH): Update.
707 (mt_asm_hash, mt_cgen_insn_supported): Renamed.
708 (parse_loopsize, parse_imm16): Adjust.
710 2005-12-13 DJ Delorie <dj@redhat.com>
712 * m32c.cpu (jsri): Fix order so register names aren't treated as
714 (indexb, indexbd, indexbs, indexl, indexld, indexls, indexw,
715 indexwd, indexws): Fix encodings.
717 2005-12-12 Nathan Sidwell <nathan@codesourcery.com>
719 * mt.cpu: Rename from ms1.cpu.
720 * mt.opc: Rename from ms1.opc.
722 2005-12-06 Hans-Peter Nilsson <hp@axis.com>
724 * cris.cpu (simplecris-common-writable-specregs)
725 (simplecris-common-readable-specregs): Split from
726 simplecris-common-specregs. All users changed.
727 (cris-implemented-writable-specregs-v0)
728 (cris-implemented-readable-specregs-v0): Similar from
729 cris-implemented-specregs-v0.
730 (cris-implemented-writable-specregs-v3)
731 (cris-implemented-readable-specregs-v3)
732 (cris-implemented-writable-specregs-v8)
733 (cris-implemented-readable-specregs-v8)
734 (cris-implemented-writable-specregs-v10)
735 (cris-implemented-readable-specregs-v10)
736 (cris-implemented-writable-specregs-v32)
737 (cris-implemented-readable-specregs-v32): Similar.
738 (bdap-32-pc, move-m-pcplus-p0, move-m-spplus-p8): New
739 insns and specializations.
741 2005-11-08 Nathan Sidwell <nathan@codesourcery.com>
744 * ms1.cpu (ms2, ms2bf): New architecture variant, cpu, machine and
746 (f-uu8, f-uu1, f-imm16l, f-loopo, f-cb1sel, f-cb2sel, f-cb1incr,
747 f-cb2incr, f-rc3): New fields.
748 (LOOP): New instruction.
749 (JAL-HAZARD): New hazard.
750 (imm16o, loopsize, imm16l, rc3, cb1sel, cb2sel, cb1incr, cb2incr):
752 (mul, muli, dbnz, iflush): Enable for ms2
753 (jal, reti): Has JAL-HAZARD.
754 (ldctxt, ldfb, stfb): Only ms1.
755 (fbcb): Only ms1,ms1-003.
756 (wfbinc, mefbinc, wfbincr, mwfbincr, fbcbincs, mfbcbincs,
757 fbcbincrs, mfbcbincrs): Enable for ms2.
758 (loop, loopu, dfbc, dwfb, fbwfb, dfbr): New ms2 insns.
759 * ms1.opc (parse_loopsize): New.
760 (parse_imm16): hi16/lo16 relocs are applicable to IMM16L.
763 2005-10-28 Dave Brolley <brolley@redhat.com>
765 Contribute the following change:
766 2003-09-24 Dave Brolley <brolley@redhat.com>
768 * frv.opc: Use CGEN_ATTR_VALUE_ENUM_TYPE in place of
769 CGEN_ATTR_VALUE_TYPE.
770 * m32c.opc (m32c_cgen_insn_supported): Use CGEN_INSN_BITSET_ATTR_VALUE.
771 Use cgen_bitset_intersect_p.
773 2005-10-27 DJ Delorie <dj@redhat.com>
775 * m32c.cpu (Imm-8-s4n, Imm-12-s4n): New.
776 (arith-jnz16-imm4-dst-defn, arith-jnz32-imm4-dst-defn,
777 arith-jnz-imm4-dst-mach, arith-jnz-imm4-dst): Keep track of which
778 imm operand is needed.
779 (adjnz, sbjnz): Pass the right operands.
780 (unary-insn-defn, unary16-defn, unary32-defn, unary-insn-mach,
781 unary-insn): Add -g variants for opcodes that need to support :G.
782 (not.BW:G, push.BW:G): Call it.
783 (stzx16-imm8-imm8-dsp8sb, stzx16-imm8-imm8-dsp8fb,
784 stzx16-imm8-imm8-abs16): Fix operand typos.
785 * m32c.opc (m32c_asm_hash): Support bnCND.
786 (parse_signed4n, print_signed4n): New.
788 2005-10-26 DJ Delorie <dj@redhat.com>
790 * m32c.cpu (f-dsp-8-s24, Dsp-8-s24): New.
791 (mov-dspsp-dst-defn, mov-src-dspsp-defn, mov16-dspsp-dst-defn,
792 mov16-src-dspsp-defn, mov32-dspsp-dst-defn, mov32-src-dspsp-defn):
794 (mov.WL:S #imm,A0/A1): dsp24 is signed (i.e. -0x800000..0xffffff).
795 (mov.BW:S r0,r1): Fix typo r1l->r1.
796 (tst): Allow :G suffix.
797 * m32c.opc (parse_signed24): New, for -0x800000..0xffffff.
799 2005-10-26 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
801 * m32r.opc (parse_hi16): Do not assume a 32-bit host word size.
803 2005-10-25 DJ Delorie <dj@redhat.com>
805 * m32c.cpu (add16-bQ-sp,add16-wQ-sp): Fix to allow either width by
806 making one a macro of the other.
808 2005-10-21 DJ Delorie <dj@redhat.com>
810 * m32c.cpu (lde, ste): Add dsp[a0] and [a1a] addressing.
811 (indexb, indexbd, indexbs, indexw, indexwd, indexws, indexl,
812 indexld, indexls): .w variants have `1' bit.
813 (rot32.b): QI, not SI.
814 (rot32.w): HI, not SI.
815 (xchg16): HI for .w variant.
817 2005-10-19 Nick Clifton <nickc@redhat.com>
819 * m32r.opc (parse_slo16): Fix bad application of previous patch.
821 2005-10-18 Andreas Schwab <schwab@suse.de>
823 * m32r.opc (parse_slo16): Better version of previous patch.
825 2005-10-14 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
827 * cpu/m32r.opc (parse_slo16): Do not assume a 32-bit host word
830 2005-07-25 DJ Delorie <dj@redhat.com>
832 * m32c.opc (parse_unsigned8): Add %dsp8().
833 (parse_signed8): Add %hi8().
834 (parse_unsigned16): Add %dsp16().
835 (parse_signed16): Add %lo16() and %hi16().
836 (parse_lab_5_3): Make valuep a bfd_vma *.
838 2005-07-18 Nick Clifton <nickc@redhat.com>
840 * m32c.cpu (f-16-8, f-24-8, f-32-16, f-dsp-8-u24): New opcode
842 (f-lab32-jmp-s): Fix insertion sequence.
843 (Dsp-8-u24, Lab-5-3, Lab32-jmp-s): New operands.
844 (Dsp-40-s8): Make parameter be signed.
845 (Dsp-40-s16): Likewise.
846 (Dsp-48-s8): Likewise.
847 (Dsp-48-s16): Likewise.
848 (Imm-13-u3): Likewise. (Despite its name!)
849 (BitBase16-16-s8): Make the parameter be unsigned.
850 (BitBase16-8-u11-S): Likewise.
851 (Lab-8-8, Lab-8-16, Lab-16-8, jcnd16-5, jcnd16, jcnd32, jmp16.s,
852 jmp16.b, jmp16.w, jmp32.s, jmp32.b, jmp32.w, jsp16.w, jsr32.w): Allow
855 * m32c.opc: Fix formatting.
856 Use safe-ctype.h instead of ctype.h
857 Move duplicated code sequences into a macro.
858 Fix compile time warnings about signedness mismatches.
860 (parse_lab_5_3): New parser function.
862 2005-07-16 Jim Blandy <jimb@redhat.com>
864 * m32c.opc (m32c_cgen_insn_supported): Use int, not CGEN_BITSET,
865 to represent isa sets.
867 2005-07-15 Jim Blandy <jimb@redhat.com>
869 * m32c.cpu, m32c.opc: Fix copyright.
871 2005-07-14 Jim Blandy <jimb@redhat.com>
873 * m32c.cpu, m32c.opc: Machine description for the Renesas M32C.
875 2005-07-14 Alan Modra <amodra@bigpond.net.au>
877 * ms1.opc (print_dollarhex): Correct format string.
879 2005-07-06 Alan Modra <amodra@bigpond.net.au>
881 * iq2000.cpu: Include from binutils cpu dir.
883 2005-07-05 Nick Clifton <nickc@redhat.com>
885 * iq2000.opc (parse_lo16, parse_mlo16): Make value parameter
886 unsigned in order to avoid compile time warnings about sign
889 * ms1.opc (parse_*): Likewise.
890 (parse_imm16): Use a "void *" as it is passed both signed and
893 2005-07-01 Nick Clifton <nickc@redhat.com>
895 * frv.opc: Update to ISO C90 function declaration style.
896 * iq2000.opc: Likewise.
897 * m32r.opc: Likewise.
900 2005-06-15 Dave Brolley <brolley@redhat.com>
902 Contributed by Red Hat.
903 * ms1.cpu: New file. Written by Nick Clifton, Stan Cox.
904 * ms1.opc: New file. Written by Stan Cox.
906 2005-05-10 Nick Clifton <nickc@redhat.com>
908 * Update the address and phone number of the FSF organization in
909 the GPL notices in the following files:
910 cris.cpu, frv.cpu, frv.opc, iq10.cpu, iq2000.opc, iq2000m.cpu,
911 m32r.cpu, m32r.opc, sh.cpu, sh.opc, sh64-compact.cpu,
912 sh64-media.cpu, simplify.inc
914 2005-02-24 Alan Modra <amodra@bigpond.net.au>
916 * frv.opc (parse_A): Warning fix.
918 2005-02-23 Nick Clifton <nickc@redhat.com>
920 * frv.opc: Fixed compile time warnings about differing signed'ness
921 of pointers passed to functions.
922 * m32r.opc: Likewise.
924 2005-02-11 Nick Clifton <nickc@redhat.com>
926 * iq2000.opc (parse_jtargq10): Change type of valuep argument to
927 'bfd_vma *' in order avoid compile time warning message.
929 2005-01-28 Hans-Peter Nilsson <hp@axis.com>
931 * cris.cpu (mstep): Add missing insn.
933 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
935 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
936 * frv.cpu: Add support for TLS annotations in loads and calll.
937 * frv.opc (parse_symbolic_address): New.
938 (parse_ldd_annotation): New.
939 (parse_call_annotation): New.
940 (parse_ld_annotation): New.
941 (parse_ulo16, parse_uslo16): Use parse_symbolic_address.
942 Introduce TLS relocations.
943 (parse_d12, parse_s12, parse_u12): Likewise.
944 (parse_uhi16): Likewise. Fix constant checking on 64-bit host.
945 (parse_call_label, print_at): New.
947 2004-12-21 Mikael Starvik <starvik@axis.com>
949 * cris.cpu (cris-set-mem): Correct integral write semantics.
951 2004-11-29 Hans-Peter Nilsson <hp@axis.com>
953 * cris.cpu: New file.
955 2004-11-15 Michael K. Lechner <mike.lechner@gmail.com>
957 * iq2000.cpu: Added quotes around macro arguments so that they
958 will work with newer versions of guile.
960 2004-10-27 Nick Clifton <nickc@redhat.com>
962 * iq2000m.cpu (pkrlr1, pkrlr30, rbr1, rbr30, rxr1, rxr30, wbr1,
963 wbr1u, wbr30, wbr30u, wxr1, wxr1u, wxr30, wxr30u): Add an index
965 * iq2000.cpu (dnop index): Rename to _index to avoid complications
968 2004-08-27 Richard Sandiford <rsandifo@redhat.com>
970 * frv.cpu (cfmovs): Change UNIT attribute to FMALL.
972 2004-05-15 Nick Clifton <nickc@redhat.com>
974 * iq2000.opc (iq2000_cgen_insn_supported): Make 'insn' argument const.
976 2004-03-30 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
978 * m32r.opc (parse_hi16): Fixed shigh(0xffff8000) bug.
980 2004-03-01 Richard Sandiford <rsandifo@redhat.com>
982 * frv.cpu (define-arch frv): Add fr450 mach.
983 (define-mach fr450): New.
984 (define-model fr450): New. Add profile units to every fr450 insn.
985 (define-attr UNIT): Add MDCUTSSI.
986 (define-attr FR450-MAJOR): New enum. Add to every fr450 insn.
987 (define-attr AUDIO): New boolean.
988 (f-LRAE, f-LRAD, f-LRAS, f-TLBPRopx, f-TLBPRL)
989 (f-LRA-null, f-TLBPR-null): New fields.
990 (scr0, scr1, scr2, scr3, imavr1, damvr1, cxnr, ttbr)
991 (tplr, tppr, tpxr, timerh, timerl, timerd, btbr): New SPRs.
992 (LRAE, LRAD, LRAS, TLBPRopx, TLBPRL): New operands.
993 (LRA-null, TLBPR-null): New macros.
994 (iacc-multiply-r-r, slass, scutss, int-arith-ss-r-r): Add AUDIO attr.
995 (load-real-address): New macro.
996 (lrai, lrad, tlbpr): New instructions.
997 (media-cut-acc, media-cut-acc-ss): Add fr450-major argument.
998 (mcut, mcuti, mcutss, mcutssi): Adjust accordingly.
999 (mdcutssi): Change UNIT attribute to MDCUTSSI.
1000 (media-low-clear-semantics, media-scope-limit-semantics)
1001 (media-quad-limit, media-quad-shift): New macros.
1002 (mqlclrhs, mqlmths, mqsllhi, mqsrahi): New instructions.
1003 * frv.opc (frv_is_branch_major, frv_is_float_major, frv_is_media_major)
1004 (frv_is_branch_insn, frv_is_float_insn, frv_is_media_insn)
1005 (frv_vliw_reset, frv_vliw_add_insn): Handle bfd_mach_fr450.
1006 (fr450_unit_mapping): New array.
1007 (fr400_unit_mapping, fr500_unit_mapping, fr550_unit_mapping): Add entry
1008 for new MDCUTSSI unit.
1009 (fr450_check_insn_major_constraints): New function.
1010 (check_insn_major_constraints): Use it.
1012 2004-03-01 Richard Sandiford <rsandifo@redhat.com>
1014 * frv.cpu (nsdiv, nudiv, nsdivi, nudivi): Remove fr400 profiling unit.
1015 (scutss): Change unit to I0.
1016 (calll, callil, ccalll): Add missing FR550-MAJOR and profile unit.
1017 (mqsaths): Fix FR400-MAJOR categorization.
1018 (media-quad-multiply-cross-acc, media-quad-cross-multiply-cross-acc)
1019 (media-quad-cross-multiply-acc): Change unit from MDUALACC to FMALL.
1020 * frv.opc (fr400_check_insn_major_constraints): Check for (M-2,M-1)
1023 2004-03-01 Richard Sandiford <rsandifo@redhat.com>
1025 * frv.cpu (r-store, r-store-dual, r-store-quad): Delete.
1026 (rstb, rsth, rst, rstd, rstq): Delete.
1027 (rstbf, rsthf, rstf, rstdf, rstqf): Delete.
1029 2004-02-23 Nick Clifton <nickc@redhat.com>
1031 * Apply these patches from Renesas:
1033 2004-02-10 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
1035 * cpu/m32r.opc (my_print_insn): Fixed incorrect output when
1036 disassembling codes for 0x*2 addresses.
1038 2003-12-15 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
1040 * cpu/m32r.cpu: Add PIPE_O attribute to "pop" instruction.
1042 2003-12-03 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
1044 * cpu/m32r.cpu : Add new model m32r2.
1045 Add new instructions.
1046 Replace occurrances of 'Mitsubishi' with 'Renesas'.
1047 Changed PIPE attr of push from O to OS.
1048 Care for Little-endian of M32R.
1049 * cpu/m32r.opc (CGEN_DIS_HASH, my_print_insn):
1050 Care for Little-endian of M32R.
1051 (parse_slo16): signed extension for value.
1053 2004-02-20 Andrew Cagney <cagney@redhat.com>
1055 * m32r.opc, m32r.cpu: New files. Written by , Doug Evans, Nick
1056 Clifton, Ben Elliston, Matthew Green, and Andrew Haley.
1058 * sh.cpu, sh.opc, sh64-compact.cpu, sh64-media.cpu: New files, all
1059 written by Ben Elliston.
1061 2004-01-14 Richard Sandiford <rsandifo@redhat.com>
1063 * frv.cpu (UNIT): Add IACC.
1064 (iacc-multiply-r-r): Use it.
1065 * frv.opc (fr400_unit_mapping): Add entry for IACC.
1066 (fr500_unit_mapping, fr550_unit_mapping): Likewise.
1068 2004-01-06 Alexandre Oliva <aoliva@redhat.com>
1070 2003-12-19 Alexandre Oliva <aoliva@redhat.com>
1071 * frv.opc (parse_ulo16, parse_uhi16, parse_d12): Fix some
1072 cut&paste errors in shifting/truncating numerical operands.
1073 2003-08-08 Alexandre Oliva <aoliva@redhat.com>
1074 * frv.opc (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
1075 (parse_uslo16): Likewise.
1076 (parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
1077 (parse_d12): Parse gotoff12 and gotofffuncdesc12.
1078 (parse_s12): Likewise.
1079 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
1080 * frv.opc (parse_ulo16): Parse gotlo and gotfuncdesclo.
1081 (parse_uslo16): Likewise.
1082 (parse_uhi16): Parse gothi and gotfuncdeschi.
1083 (parse_d12): Parse got12 and gotfuncdesc12.
1084 (parse_s12): Likewise.
1086 2003-10-10 Dave Brolley <brolley@redhat.com>
1088 * frv.cpu (dnpmop): New p-macro.
1089 (GRdoublek): Use dnpmop.
1090 (CPRdoublek, FRdoublei, FRdoublej, FRdoublek): Ditto.
1091 (store-double-r-r): Use (.sym regtype doublek).
1092 (r-store-double): Ditto.
1093 (store-double-r-r-u): Ditto.
1094 (conditional-store-double): Ditto.
1095 (conditional-store-double-u): Ditto.
1096 (store-double-r-simm): Ditto.
1097 (fmovs): Assign to UNIT FMALL.
1099 2003-10-06 Dave Brolley <brolley@redhat.com>
1101 * frv.cpu, frv.opc: Add support for fr550.
1103 2003-09-24 Dave Brolley <brolley@redhat.com>
1105 * frv.cpu (u-commit): New modelling unit for fr500.
1106 (mwtaccg): Use frv_ref_SI to reference ACC40Sk as an input operand.
1107 (commit-r): Use u-commit model for fr500.
1109 (conditional-float-binary-op): Take profiling data as an argument.
1111 (ne-float-binary-op): Ditto.
1113 2003-09-19 Michael Snyder <msnyder@redhat.com>
1115 * frv.cpu (nldqi): Delete unimplemented instruction.
1117 2003-09-12 Dave Brolley <brolley@redhat.com>
1119 * frv.cpu (u-clrgr, u-clrfr): New units of model fr500.
1120 (clear-ne-flag-r): Pass insn profiling in as an argument. Call
1121 frv_ref_SI to get input register referenced for profiling.
1122 (clear-ne-flag-all): Pass insn profiling in as an argument.
1123 (clrgr,clrfr,clrga,clrfa): Add profiling information.
1125 2003-09-11 Michael Snyder <msnyder@redhat.com>
1127 * frv.cpu: Typographical corrections.
1129 2003-09-09 Dave Brolley <brolley@redhat.com>
1131 * frv.cpu (media-dual-complex): Change UNIT to FMALL.
1132 (conditional-media-dual-complex, media-quad-complex): Likewise.
1134 2003-09-04 Dave Brolley <brolley@redhat.com>
1136 * frv.cpu (register-transfer): Pass in all attributes in on argument.
1138 (conditional-register-transfer): Ditto.
1139 (cache-preload): Ditto.
1140 (floating-point-conversion): Ditto.
1141 (floating-point-neg): Ditto.
1143 (float-binary-op-s): Ditto.
1144 (conditional-float-binary-op): Ditto.
1145 (ne-float-binary-op): Ditto.
1146 (float-dual-arith): Ditto.
1147 (ne-float-dual-arith): Ditto.
1149 2003-09-03 Dave Brolley <brolley@redhat.com>
1151 * frv.opc (parse_A, parse_A0, parse_A1): New parse handlers.
1152 * frv.cpu (UNIT): Add IALL, FMALL, FMLOW, STORE, SCAN, DCPL, MDUALACC,
1154 (A): Removed operand.
1155 (A0,A1): New operands replace operand A.
1156 (mnop): Now a real insn
1157 (mclracc): Removed insn.
1158 (mclracc-0, mclracc-1): New insns replace mclracc.
1159 (all insns): Use new UNIT attributes.
1161 2003-08-21 Nick Clifton <nickc@redhat.com>
1163 * frv.cpu (mbtoh): Replace input parameter to u-media-dual-expand
1164 and u-media-dual-btoh with output parameter.
1165 (cmbtoh): Add profiling hack.
1167 2003-08-19 Michael Snyder <msnyder@redhat.com>
1169 * frv.cpu: Fix typo, Frintkeven -> FRintkeven
1171 2003-06-10 Doug Evans <dje@sebabeach.org>
1173 * frv.cpu: Add IDOC attribute.
1175 2003-06-06 Andrew Cagney <cagney@redhat.com>
1177 Contributed by Red Hat.
1178 * iq2000.cpu: New file. Written by Ben Elliston, Jeff Johnston,
1179 Stan Cox, and Frank Ch. Eigler.
1180 * iq2000.opc: New file. Written by Ben Elliston, Frank
1181 Ch. Eigler, Chris Moller, Jeff Johnston, and Stan Cox.
1182 * iq2000m.cpu: New file. Written by Jeff Johnston.
1183 * iq10.cpu: New file. Written by Jeff Johnston.
1185 2003-06-05 Nick Clifton <nickc@redhat.com>
1187 * frv.cpu (FRintieven): New operand. An even-numbered only
1188 version of the FRinti operand.
1189 (FRintjeven): Likewise for FRintj.
1190 (FRintkeven): Likewise for FRintk.
1191 (mdcutssi, media-dual-word-rotate-r-r, mqsaths,
1192 media-quad-arith-sat-semantics, media-quad-arith-sat,
1193 conditional-media-quad-arith-sat, mdunpackh,
1194 media-quad-multiply-semantics, media-quad-multiply,
1195 conditional-media-quad-multiply, media-quad-complex-i,
1196 media-quad-multiply-acc-semantics, media-quad-multiply-acc,
1197 conditional-media-quad-multiply-acc, munpackh,
1198 media-quad-multiply-cross-acc-semantics, mdpackh,
1199 media-quad-multiply-cross-acc, mbtoh-semantics,
1200 media-quad-cross-multiply-cross-acc-semantics,
1201 media-quad-cross-multiply-cross-acc, mbtoh, mhtob-semantics,
1202 media-quad-cross-multiply-acc-semantics, cmbtoh,
1203 media-quad-cross-multiply-acc, media-quad-complex, mhtob,
1204 media-expand-halfword-to-double-semantics, mexpdhd, cmexpdhd,
1205 cmhtob): Use new operands.
1206 * frv.opc (CGEN_VERBOSE_ASSEMBLER_ERRORS): Define.
1207 (parse_even_register): New function.
1209 2003-06-03 Nick Clifton <nickc@redhat.com>
1211 * frv.cpu (media-dual-word-rotate-r-r): Use a signed 6-bit
1212 immediate value not unsigned.
1214 2003-06-03 Andrew Cagney <cagney@redhat.com>
1216 Contributed by Red Hat.
1217 * frv.cpu: New file. Written by Dave Brolley, Catherine Moore,
1218 and Eric Christopher.
1219 * frv.opc: New file. Written by Catherine Moore, and Dave
1221 * simplify.inc: New file. Written by Doug Evans.
1223 2003-05-02 Andrew Cagney <cagney@redhat.com>
1228 Copyright (C) 2003-2012 Free Software Foundation, Inc.
1230 Copying and distribution of this file, with or without modification,
1231 are permitted in any medium without royalty provided the copyright
1232 notice and this notice are preserved.
1238 version-control: never