cpu/base_cpu.cc

   1 /*
   2  * Copyright (c) 2003 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #include <string>
  30 #include <sstream>
  31 #include <iostream>
  32
  33 #include "cpu/base_cpu.hh"
  34 #include "base/cprintf.hh"
  35 #include "cpu/exec_context.hh"
  36 #include "base/misc.hh"
  37 #include "sim/sim_events.hh"
  38
  39 using namespace std;
  40
  41 vector<BaseCPU *> BaseCPU::cpuList;
  42
  43 // This variable reflects the max number of threads in any CPU.  Be
  44 // careful to only use it once all the CPUs that you care about have
  45 // been initialized
  46 int maxThreadsPerCPU = 1;
  47
  48 #ifdef FULL_SYSTEM
  49 BaseCPU::BaseCPU(const string &_name, int _number_of_threads,
  50                  Counter max_insts_any_thread,
  51                  Counter max_insts_all_threads,
  52                  Counter max_loads_any_thread,
  53                  Counter max_loads_all_threads,
  54                  System *_system, int num, Tick freq)
  55     : SimObject(_name), number(num), frequency(freq),
  56       number_of_threads(_number_of_threads), system(_system)
  57 #else
  58 BaseCPU::BaseCPU(const string &_name, int _number_of_threads,
  59                  Counter max_insts_any_thread,
  60                  Counter max_insts_all_threads,
  61                  Counter max_loads_any_thread,
  62                  Counter max_loads_all_threads)
  63     : SimObject(_name), number_of_threads(_number_of_threads)
  64 #endif
  65 {
  66     // add self to global list of CPUs
  67     cpuList.push_back(this);
  68
  69     if (number_of_threads > maxThreadsPerCPU)
  70         maxThreadsPerCPU = number_of_threads;
  71
  72     // allocate per-thread instruction-based event queues
  73     comInsnEventQueue = new (EventQueue *)[number_of_threads];
  74     for (int i = 0; i < number_of_threads; ++i)
  75         comInsnEventQueue[i] = new EventQueue("instruction-based event queue");
  76
  77     //
  78     // set up instruction-count-based termination events, if any
  79     //
  80     if (max_insts_any_thread != 0)
  81         for (int i = 0; i < number_of_threads; ++i)
  82             new SimExitEvent(comInsnEventQueue[i], max_insts_any_thread,
  83                 "a thread reached the max instruction count");
  84
  85     if (max_insts_all_threads != 0) {
  86         // allocate & initialize shared downcounter: each event will
  87         // decrement this when triggered; simulation will terminate
  88         // when counter reaches 0
  89         int *counter = new int;
  90         *counter = number_of_threads;
  91         for (int i = 0; i < number_of_threads; ++i)
  92             new CountedExitEvent(comInsnEventQueue[i],
  93                 "all threads reached the max instruction count",
  94                 max_insts_all_threads, *counter);
  95     }
  96
  97     // allocate per-thread load-based event queues
  98     comLoadEventQueue = new (EventQueue *)[number_of_threads];
  99     for (int i = 0; i < number_of_threads; ++i)
 100         comLoadEventQueue[i] = new EventQueue("load-based event queue");
 101
 102     //
 103     // set up instruction-count-based termination events, if any
 104     //
 105     if (max_loads_any_thread != 0)
 106         for (int i = 0; i < number_of_threads; ++i)
 107             new SimExitEvent(comLoadEventQueue[i], max_loads_any_thread,
 108                 "a thread reached the max load count");
 109
 110     if (max_loads_all_threads != 0) {
 111         // allocate & initialize shared downcounter: each event will
 112         // decrement this when triggered; simulation will terminate
 113         // when counter reaches 0
 114         int *counter = new int;
 115         *counter = number_of_threads;
 116         for (int i = 0; i < number_of_threads; ++i)
 117             new CountedExitEvent(comLoadEventQueue[i],
 118                 "all threads reached the max load count",
 119                 max_loads_all_threads, *counter);
 120     }
 121
 122
 123 #ifdef FULL_SYSTEM
 124     memset(interrupts, 0, sizeof(interrupts));
 125     intstatus = 0;
 126 #endif
 127 }
 128
 129 void
 130 BaseCPU::regStats()
 131 {
 132     int size = contexts.size();
 133     if (size > 1) {
 134         for (int i = 0; i < size; ++i) {
 135             stringstream namestr;
 136             ccprintf(namestr, "%s.ctx%d", name(), i);
 137             contexts[i]->regStats(namestr.str());
 138         }
 139     } else if (size == 1)
 140         contexts[0]->regStats(name());
 141 }
 142
 143 #ifdef FULL_SYSTEM
 144 void
 145 BaseCPU::post_interrupt(int int_num, int index)
 146 {
 147     DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index);
 148
 149     if (int_num < 0 || int_num >= NumInterruptLevels)
 150         panic("int_num out of bounds\n");
 151
 152     if (index < 0 || index >= sizeof(uint8_t) * 8)
 153         panic("int_num out of bounds\n");
 154
 155     AlphaISA::check_interrupts = 1;
 156     interrupts[int_num] |= 1 << index;
 157     intstatus |= (ULL(1) << int_num);
 158 }
 159
 160 void
 161 BaseCPU::clear_interrupt(int int_num, int index)
 162 {
 163     DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index);
 164
 165     if (int_num < 0 || int_num >= NumInterruptLevels)
 166         panic("int_num out of bounds\n");
 167
 168     if (index < 0 || index >= sizeof(uint8_t) * 8)
 169         panic("int_num out of bounds\n");
 170
 171     interrupts[int_num] &= ~(1 << index);
 172     if (interrupts[int_num] == 0)
 173         intstatus &= ~(ULL(1) << int_num);
 174 }
 175
 176 void
 177 BaseCPU::clear_interrupts()
 178 {
 179     DPRINTF(Interrupt, "Interrupts all cleared\n");
 180
 181     memset(interrupts, 0, sizeof(interrupts));
 182     intstatus = 0;
 183 }
 184
 185 #endif // FULL_SYSTEM
 186
 187 DEFINE_SIM_OBJECT_CLASS_NAME("BaseCPU", BaseCPU)