2 * Copyright (c) 2003 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 #include "cpu/base_cpu.hh"
34 #include "base/cprintf.hh"
35 #include "cpu/exec_context.hh"
36 #include "base/misc.hh"
37 #include "sim/param.hh"
38 #include "sim/sim_events.hh"
42 vector
<BaseCPU
*> BaseCPU::cpuList
;
44 // This variable reflects the max number of threads in any CPU. Be
45 // careful to only use it once all the CPUs that you care about have
47 int maxThreadsPerCPU
= 1;
50 BaseCPU::BaseCPU(const string
&_name
, int _number_of_threads
,
51 Counter max_insts_any_thread
,
52 Counter max_insts_all_threads
,
53 Counter max_loads_any_thread
,
54 Counter max_loads_all_threads
,
55 System
*_system
, Tick freq
)
56 : SimObject(_name
), frequency(freq
),
57 number_of_threads(_number_of_threads
), system(_system
)
59 BaseCPU::BaseCPU(const string
&_name
, int _number_of_threads
,
60 Counter max_insts_any_thread
,
61 Counter max_insts_all_threads
,
62 Counter max_loads_any_thread
,
63 Counter max_loads_all_threads
)
64 : SimObject(_name
), number_of_threads(_number_of_threads
)
67 // add self to global list of CPUs
68 cpuList
.push_back(this);
70 if (number_of_threads
> maxThreadsPerCPU
)
71 maxThreadsPerCPU
= number_of_threads
;
73 // allocate per-thread instruction-based event queues
74 comInstEventQueue
= new (EventQueue
*)[number_of_threads
];
75 for (int i
= 0; i
< number_of_threads
; ++i
)
76 comInstEventQueue
[i
] = new EventQueue("instruction-based event queue");
79 // set up instruction-count-based termination events, if any
81 if (max_insts_any_thread
!= 0)
82 for (int i
= 0; i
< number_of_threads
; ++i
)
83 new SimExitEvent(comInstEventQueue
[i
], max_insts_any_thread
,
84 "a thread reached the max instruction count");
86 if (max_insts_all_threads
!= 0) {
87 // allocate & initialize shared downcounter: each event will
88 // decrement this when triggered; simulation will terminate
89 // when counter reaches 0
90 int *counter
= new int;
91 *counter
= number_of_threads
;
92 for (int i
= 0; i
< number_of_threads
; ++i
)
93 new CountedExitEvent(comInstEventQueue
[i
],
94 "all threads reached the max instruction count",
95 max_insts_all_threads
, *counter
);
98 // allocate per-thread load-based event queues
99 comLoadEventQueue
= new (EventQueue
*)[number_of_threads
];
100 for (int i
= 0; i
< number_of_threads
; ++i
)
101 comLoadEventQueue
[i
] = new EventQueue("load-based event queue");
104 // set up instruction-count-based termination events, if any
106 if (max_loads_any_thread
!= 0)
107 for (int i
= 0; i
< number_of_threads
; ++i
)
108 new SimExitEvent(comLoadEventQueue
[i
], max_loads_any_thread
,
109 "a thread reached the max load count");
111 if (max_loads_all_threads
!= 0) {
112 // allocate & initialize shared downcounter: each event will
113 // decrement this when triggered; simulation will terminate
114 // when counter reaches 0
115 int *counter
= new int;
116 *counter
= number_of_threads
;
117 for (int i
= 0; i
< number_of_threads
; ++i
)
118 new CountedExitEvent(comLoadEventQueue
[i
],
119 "all threads reached the max load count",
120 max_loads_all_threads
, *counter
);
124 memset(interrupts
, 0, sizeof(interrupts
));
133 using namespace Stats
;
136 .name(name() + ".numCycles")
137 .desc("number of cpu cycles simulated")
140 int size
= execContexts
.size();
142 for (int i
= 0; i
< size
; ++i
) {
143 stringstream namestr
;
144 ccprintf(namestr
, "%s.ctx%d", name(), i
);
145 execContexts
[i
]->regStats(namestr
.str());
147 } else if (size
== 1)
148 execContexts
[0]->regStats(name());
153 BaseCPU::registerExecContexts()
155 for (int i
= 0; i
< execContexts
.size(); ++i
) {
156 ExecContext
*xc
= execContexts
[i
];
160 cpu_id
= system
->registerExecContext(xc
);
162 cpu_id
= xc
->process
->registerExecContext(xc
);
173 // default: do nothing
177 BaseCPU::takeOverFrom(BaseCPU
*oldCPU
)
179 assert(execContexts
.size() == oldCPU
->execContexts
.size());
181 for (int i
= 0; i
< execContexts
.size(); ++i
) {
182 ExecContext
*newXC
= execContexts
[i
];
183 ExecContext
*oldXC
= oldCPU
->execContexts
[i
];
185 newXC
->takeOverFrom(oldXC
);
186 assert(newXC
->cpu_id
== oldXC
->cpu_id
);
188 system
->replaceExecContext(newXC
->cpu_id
, newXC
);
190 assert(newXC
->process
== oldXC
->process
);
191 newXC
->process
->replaceExecContext(newXC
->cpu_id
, newXC
);
196 for (int i
= 0; i
< NumInterruptLevels
; ++i
)
197 interrupts
[i
] = oldCPU
->interrupts
[i
];
198 intstatus
= oldCPU
->intstatus
;
205 BaseCPU::post_interrupt(int int_num
, int index
)
207 DPRINTF(Interrupt
, "Interrupt %d:%d posted\n", int_num
, index
);
209 if (int_num
< 0 || int_num
>= NumInterruptLevels
)
210 panic("int_num out of bounds\n");
212 if (index
< 0 || index
>= sizeof(uint64_t) * 8)
213 panic("int_num out of bounds\n");
215 AlphaISA::check_interrupts
= 1;
216 interrupts
[int_num
] |= 1 << index
;
217 intstatus
|= (ULL(1) << int_num
);
221 BaseCPU::clear_interrupt(int int_num
, int index
)
223 DPRINTF(Interrupt
, "Interrupt %d:%d cleared\n", int_num
, index
);
225 if (int_num
< 0 || int_num
>= NumInterruptLevels
)
226 panic("int_num out of bounds\n");
228 if (index
< 0 || index
>= sizeof(uint64_t) * 8)
229 panic("int_num out of bounds\n");
231 interrupts
[int_num
] &= ~(1 << index
);
232 if (interrupts
[int_num
] == 0)
233 intstatus
&= ~(ULL(1) << int_num
);
237 BaseCPU::clear_interrupts()
239 DPRINTF(Interrupt
, "Interrupts all cleared\n");
241 memset(interrupts
, 0, sizeof(interrupts
));
245 #endif // FULL_SYSTEM
247 DEFINE_SIM_OBJECT_CLASS_NAME("BaseCPU", BaseCPU
)