cpu/base_cpu.cc

   1 /*
   2  * Copyright (c) 2003 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #include <string>
  30 #include <sstream>
  31 #include <iostream>
  32
  33 #include "cpu/base_cpu.hh"
  34 #include "base/cprintf.hh"
  35 #include "cpu/exec_context.hh"
  36 #include "base/misc.hh"
  37 #include "sim/param.hh"
  38 #include "sim/sim_events.hh"
  39
  40 using namespace std;
  41
  42 vector<BaseCPU *> BaseCPU::cpuList;
  43
  44 // This variable reflects the max number of threads in any CPU.  Be
  45 // careful to only use it once all the CPUs that you care about have
  46 // been initialized
  47 int maxThreadsPerCPU = 1;
  48
  49 #ifdef FULL_SYSTEM
  50 BaseCPU::BaseCPU(const string &_name, int _number_of_threads,
  51                  Counter max_insts_any_thread,
  52                  Counter max_insts_all_threads,
  53                  Counter max_loads_any_thread,
  54                  Counter max_loads_all_threads,
  55                  System *_system, int num, Tick freq)
  56     : SimObject(_name), number(num), frequency(freq),
  57       number_of_threads(_number_of_threads), system(_system)
  58 #else
  59 BaseCPU::BaseCPU(const string &_name, int _number_of_threads,
  60                  Counter max_insts_any_thread,
  61                  Counter max_insts_all_threads,
  62                  Counter max_loads_any_thread,
  63                  Counter max_loads_all_threads)
  64     : SimObject(_name), number_of_threads(_number_of_threads)
  65 #endif
  66 {
  67     // add self to global list of CPUs
  68     cpuList.push_back(this);
  69
  70     if (number_of_threads > maxThreadsPerCPU)
  71         maxThreadsPerCPU = number_of_threads;
  72
  73     // allocate per-thread instruction-based event queues
  74     comInsnEventQueue = new (EventQueue *)[number_of_threads];
  75     for (int i = 0; i < number_of_threads; ++i)
  76         comInsnEventQueue[i] = new EventQueue("instruction-based event queue");
  77
  78     //
  79     // set up instruction-count-based termination events, if any
  80     //
  81     if (max_insts_any_thread != 0)
  82         for (int i = 0; i < number_of_threads; ++i)
  83             new SimExitEvent(comInsnEventQueue[i], max_insts_any_thread,
  84                 "a thread reached the max instruction count");
  85
  86     if (max_insts_all_threads != 0) {
  87         // allocate & initialize shared downcounter: each event will
  88         // decrement this when triggered; simulation will terminate
  89         // when counter reaches 0
  90         int *counter = new int;
  91         *counter = number_of_threads;
  92         for (int i = 0; i < number_of_threads; ++i)
  93             new CountedExitEvent(comInsnEventQueue[i],
  94                 "all threads reached the max instruction count",
  95                 max_insts_all_threads, *counter);
  96     }
  97
  98     // allocate per-thread load-based event queues
  99     comLoadEventQueue = new (EventQueue *)[number_of_threads];
 100     for (int i = 0; i < number_of_threads; ++i)
 101         comLoadEventQueue[i] = new EventQueue("load-based event queue");
 102
 103     //
 104     // set up instruction-count-based termination events, if any
 105     //
 106     if (max_loads_any_thread != 0)
 107         for (int i = 0; i < number_of_threads; ++i)
 108             new SimExitEvent(comLoadEventQueue[i], max_loads_any_thread,
 109                 "a thread reached the max load count");
 110
 111     if (max_loads_all_threads != 0) {
 112         // allocate & initialize shared downcounter: each event will
 113         // decrement this when triggered; simulation will terminate
 114         // when counter reaches 0
 115         int *counter = new int;
 116         *counter = number_of_threads;
 117         for (int i = 0; i < number_of_threads; ++i)
 118             new CountedExitEvent(comLoadEventQueue[i],
 119                 "all threads reached the max load count",
 120                 max_loads_all_threads, *counter);
 121     }
 122
 123
 124 #ifdef FULL_SYSTEM
 125     memset(interrupts, 0, sizeof(interrupts));
 126     intstatus = 0;
 127 #endif
 128 }
 129
 130 void
 131 BaseCPU::regStats()
 132 {
 133     int size = contexts.size();
 134     if (size > 1) {
 135         for (int i = 0; i < size; ++i) {
 136             stringstream namestr;
 137             ccprintf(namestr, "%s.ctx%d", name(), i);
 138             contexts[i]->regStats(namestr.str());
 139         }
 140     } else if (size == 1)
 141         contexts[0]->regStats(name());
 142 }
 143
 144 #ifdef FULL_SYSTEM
 145 void
 146 BaseCPU::post_interrupt(int int_num, int index)
 147 {
 148     DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index);
 149
 150     if (int_num < 0 || int_num >= NumInterruptLevels)
 151         panic("int_num out of bounds\n");
 152
 153     if (index < 0 || index >= sizeof(uint8_t) * 8)
 154         panic("int_num out of bounds\n");
 155
 156     AlphaISA::check_interrupts = 1;
 157     interrupts[int_num] |= 1 << index;
 158     intstatus |= (ULL(1) << int_num);
 159 }
 160
 161 void
 162 BaseCPU::clear_interrupt(int int_num, int index)
 163 {
 164     DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index);
 165
 166     if (int_num < 0 || int_num >= NumInterruptLevels)
 167         panic("int_num out of bounds\n");
 168
 169     if (index < 0 || index >= sizeof(uint8_t) * 8)
 170         panic("int_num out of bounds\n");
 171
 172     interrupts[int_num] &= ~(1 << index);
 173     if (interrupts[int_num] == 0)
 174         intstatus &= ~(ULL(1) << int_num);
 175 }
 176
 177 void
 178 BaseCPU::clear_interrupts()
 179 {
 180     DPRINTF(Interrupt, "Interrupts all cleared\n");
 181
 182     memset(interrupts, 0, sizeof(interrupts));
 183     intstatus = 0;
 184 }
 185
 186 #endif // FULL_SYSTEM
 187
 188 DEFINE_SIM_OBJECT_CLASS_NAME("BaseCPU", BaseCPU)