cpu/base_cpu.hh

   1 /*
   2  * Copyright (c) 2002-2004 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #ifndef __BASE_CPU_HH__
  30 #define __BASE_CPU_HH__
  31
  32 #include <vector>
  33
  34 #include "base/statistics.hh"
  35 #include "sim/eventq.hh"
  36 #include "sim/sim_object.hh"
  37 #include "targetarch/isa_traits.hh"
  38
  39 #ifdef FULL_SYSTEM
  40 class System;
  41 #endif
  42
  43 class BranchPred;
  44 class ExecContext;
  45
  46 class BaseCPU : public SimObject
  47 {
  48 #ifdef FULL_SYSTEM
  49   protected:
  50     Tick frequency;
  51     uint64_t interrupts[NumInterruptLevels];
  52     uint64_t intstatus;
  53
  54   public:
  55     virtual void post_interrupt(int int_num, int index);
  56     virtual void clear_interrupt(int int_num, int index);
  57     virtual void clear_interrupts();
  58     bool checkInterrupts;
  59
  60     bool check_interrupt(int int_num) const {
  61         if (int_num > NumInterruptLevels)
  62             panic("int_num out of bounds\n");
  63
  64         return interrupts[int_num] != 0;
  65     }
  66
  67     bool check_interrupts() const { return intstatus != 0; }
  68     uint64_t intr_status() const { return intstatus; }
  69
  70     Tick getFreq() const { return frequency; }
  71 #endif
  72
  73   protected:
  74     std::vector<ExecContext *> execContexts;
  75
  76   public:
  77
  78     /// Notify the CPU that the indicated context is now active.  The
  79     /// delay parameter indicates the number of ticks to wait before
  80     /// executing (typically 0 or 1).
  81     virtual void activateContext(int thread_num, int delay) {}
  82
  83     /// Notify the CPU that the indicated context is now suspended.
  84     virtual void suspendContext(int thread_num) {}
  85
  86     /// Notify the CPU that the indicated context is now deallocated.
  87     virtual void deallocateContext(int thread_num) {}
  88
  89     /// Notify the CPU that the indicated context is now halted.
  90     virtual void haltContext(int thread_num) {}
  91
  92   public:
  93
  94 #ifdef FULL_SYSTEM
  95     BaseCPU(const std::string &_name, int _number_of_threads, bool _def_reg,
  96             Counter max_insts_any_thread, Counter max_insts_all_threads,
  97             Counter max_loads_any_thread, Counter max_loads_all_threads,
  98             System *_system, Tick freq);
  99 #else
 100     BaseCPU(const std::string &_name, int _number_of_threads, bool _def_reg,
 101             Counter max_insts_any_thread = 0,
 102             Counter max_insts_all_threads = 0,
 103             Counter max_loads_any_thread = 0,
 104             Counter max_loads_all_threads = 0);
 105 #endif
 106
 107     virtual ~BaseCPU() {}
 108
 109     virtual void init();
 110     virtual void regStats();
 111
 112     bool deferRegistration;
 113     void registerExecContexts();
 114
 115     /// Prepare for another CPU to take over execution.  Called by
 116     /// takeOverFrom() on its argument.
 117     virtual void switchOut();
 118
 119     /// Take over execution from the given CPU.  Used for warm-up and
 120     /// sampling.
 121     virtual void takeOverFrom(BaseCPU *);
 122
 123     /**
 124      *  Number of threads we're actually simulating (<= SMT_MAX_THREADS).
 125      * This is a constant for the duration of the simulation.
 126      */
 127     int number_of_threads;
 128
 129     /**
 130      * Vector of per-thread instruction-based event queues.  Used for
 131      * scheduling events based on number of instructions committed by
 132      * a particular thread.
 133      */
 134     EventQueue **comInstEventQueue;
 135
 136     /**
 137      * Vector of per-thread load-based event queues.  Used for
 138      * scheduling events based on number of loads committed by
 139      *a particular thread.
 140      */
 141     EventQueue **comLoadEventQueue;
 142
 143 #ifdef FULL_SYSTEM
 144     System *system;
 145
 146     /**
 147      * Serialize this object to the given output stream.
 148      * @param os The stream to serialize to.
 149      */
 150     virtual void serialize(std::ostream &os);
 151
 152     /**
 153      * Reconstruct the state of this object from a checkpoint.
 154      * @param cp The checkpoint use.
 155      * @param section The section name of this object
 156      */
 157     virtual void unserialize(Checkpoint *cp, const std::string &section);
 158
 159 #endif
 160
 161     /**
 162      * Return pointer to CPU's branch predictor (NULL if none).
 163      * @return Branch predictor pointer.
 164      */
 165     virtual BranchPred *getBranchPred() { return NULL; };
 166
 167     virtual Counter totalInstructions() const { return 0; }
 168
 169   private:
 170     static std::vector<BaseCPU *> cpuList;   //!< Static global cpu list
 171
 172   public:
 173     static int numSimulatedCPUs() { return cpuList.size(); }
 174     static Counter numSimulatedInstructions()
 175     {
 176         Counter total = 0;
 177
 178         int size = cpuList.size();
 179         for (int i = 0; i < size; ++i)
 180             total += cpuList[i]->totalInstructions();
 181
 182         return total;
 183     }
 184
 185   public:
 186     // Number of CPU cycles simulated
 187     Stats::Scalar<> numCycles;
 188 };
 189
 190 #endif // __BASE_CPU_HH__