cpu/base_dyn_inst.hh

   1 /*
   2  * Copyright (c) 2004-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #ifndef __CPU_BASE_DYN_INST_HH__
  30 #define __CPU_BASE_DYN_INST_HH__
  31
  32 #include <string>
  33 #include <vector>
  34
  35 #include "base/fast_alloc.hh"
  36 #include "base/trace.hh"
  37 #include "config/full_system.hh"
  38 #include "cpu/exetrace.hh"
  39 #include "cpu/inst_seq.hh"
  40 #include "cpu/o3/comm.hh"
  41 #include "cpu/static_inst.hh"
  42 #include "encumbered/cpu/full/bpred_update.hh"
  43 #include "encumbered/cpu/full/op_class.hh"
  44 #include "encumbered/cpu/full/spec_memory.hh"
  45 #include "encumbered/cpu/full/spec_state.hh"
  46 #include "encumbered/mem/functional/main.hh"
  47
  48 /**
  49  * @file
  50  * Defines a dynamic instruction context.
  51  */
  52
  53 // Forward declaration.
  54 class StaticInstPtr;
  55
  56 template <class Impl>
  57 class BaseDynInst : public FastAlloc, public RefCounted
  58 {
  59   public:
  60     // Typedef for the CPU.
  61     typedef typename Impl::FullCPU FullCPU;
  62
  63     /// Binary machine instruction type.
  64     typedef TheISA::MachInst MachInst;
  65     /// Logical register index type.
  66     typedef TheISA::RegIndex RegIndex;
  67     /// Integer register index type.
  68     typedef TheISA::IntReg IntReg;
  69
  70     enum {
  71         MaxInstSrcRegs = TheISA::MaxInstSrcRegs,        //< Max source regs
  72         MaxInstDestRegs = TheISA::MaxInstDestRegs,      //< Max dest regs
  73     };
  74
  75     /** The static inst used by this dyn inst. */
  76     StaticInstPtr staticInst;
  77
  78     ////////////////////////////////////////////
  79     //
  80     // INSTRUCTION EXECUTION
  81     //
  82     ////////////////////////////////////////////
  83     Trace::InstRecord *traceData;
  84
  85     template <class T>
  86     Fault read(Addr addr, T &data, unsigned flags);
  87
  88     template <class T>
  89     Fault write(T data, Addr addr, unsigned flags,
  90                         uint64_t *res);
  91
  92     void prefetch(Addr addr, unsigned flags);
  93     void writeHint(Addr addr, int size, unsigned flags);
  94     Fault copySrcTranslate(Addr src);
  95     Fault copy(Addr dest);
  96
  97     /** @todo: Consider making this private. */
  98   public:
  99     /** Is this instruction valid. */
 100     bool valid;
 101
 102     /** The sequence number of the instruction. */
 103     InstSeqNum seqNum;
 104
 105     /** How many source registers are ready. */
 106     unsigned readyRegs;
 107
 108     /** Is the instruction completed. */
 109     bool completed;
 110
 111     /** Can this instruction issue. */
 112     bool canIssue;
 113
 114     /** Has this instruction issued. */
 115     bool issued;
 116
 117     /** Has this instruction executed (or made it through execute) yet. */
 118     bool executed;
 119
 120     /** Can this instruction commit. */
 121     bool canCommit;
 122
 123     /** Is this instruction squashed. */
 124     bool squashed;
 125
 126     /** Is this instruction squashed in the instruction queue. */
 127     bool squashedInIQ;
 128
 129     /** Is this a recover instruction. */
 130     bool recoverInst;
 131
 132     /** Is this a thread blocking instruction. */
 133     bool blockingInst;  /* this inst has called thread_block() */
 134
 135     /** Is this a thread syncrhonization instruction. */
 136     bool threadsyncWait;
 137
 138     /** The thread this instruction is from. */
 139     short threadNumber;
 140
 141     /** data address space ID, for loads & stores. */
 142     short asid;
 143
 144     /** Pointer to the FullCPU object. */
 145     FullCPU *cpu;
 146
 147     /** Pointer to the exec context.  Will not exist in the final version. */
 148     CPUExecContext *cpuXC;
 149
 150     /** The kind of fault this instruction has generated. */
 151     Fault fault;
 152
 153     /** The effective virtual address (lds & stores only). */
 154     Addr effAddr;
 155
 156     /** The effective physical address. */
 157     Addr physEffAddr;
 158
 159     /** Effective virtual address for a copy source. */
 160     Addr copySrcEffAddr;
 161
 162     /** Effective physical address for a copy source. */
 163     Addr copySrcPhysEffAddr;
 164
 165     /** The memory request flags (from translation). */
 166     unsigned memReqFlags;
 167
 168     /** The size of the data to be stored. */
 169     int storeSize;
 170
 171     /** The data to be stored. */
 172     IntReg storeData;
 173
 174     union Result {
 175         uint64_t integer;
 176         float fp;
 177         double dbl;
 178     };
 179
 180     /** The result of the instruction; assumes for now that there's only one
 181      *  destination register.
 182      */
 183     Result instResult;
 184
 185     /** PC of this instruction. */
 186     Addr PC;
 187
 188     /** Next non-speculative PC.  It is not filled in at fetch, but rather
 189      *  once the target of the branch is truly known (either decode or
 190      *  execute).
 191      */
 192     Addr nextPC;
 193
 194     /** Predicted next PC. */
 195     Addr predPC;
 196
 197     /** Count of total number of dynamic instructions. */
 198     static int instcount;
 199
 200     /** Whether or not the source register is ready.  Not sure this should be
 201      *  here vs. the derived class.
 202      */
 203     bool _readySrcRegIdx[MaxInstSrcRegs];
 204
 205   public:
 206     /** BaseDynInst constructor given a binary instruction. */
 207     BaseDynInst(MachInst inst, Addr PC, Addr Pred_PC, InstSeqNum seq_num,
 208                 FullCPU *cpu);
 209
 210     /** BaseDynInst constructor given a static inst pointer. */
 211     BaseDynInst(StaticInstPtr &_staticInst);
 212
 213     /** BaseDynInst destructor. */
 214     ~BaseDynInst();
 215
 216   private:
 217     /** Function to initialize variables in the constructors. */
 218     void initVars();
 219
 220   public:
 221     void
 222     trace_mem(Fault fault,      // last fault
 223               MemCmd cmd,       // last command
 224               Addr addr,        // virtual address of access
 225               void *p,          // memory accessed
 226               int nbytes);      // access size
 227
 228     /** Dumps out contents of this BaseDynInst. */
 229     void dump();
 230
 231     /** Dumps out contents of this BaseDynInst into given string. */
 232     void dump(std::string &outstring);
 233
 234     /** Returns the fault type. */
 235     Fault getFault() { return fault; }
 236
 237     /** Checks whether or not this instruction has had its branch target
 238      *  calculated yet.  For now it is not utilized and is hacked to be
 239      *  always false.
 240      */
 241     bool doneTargCalc() { return false; }
 242
 243     /** Returns the next PC.  This could be the speculative next PC if it is
 244      *  called prior to the actual branch target being calculated.
 245      */
 246     Addr readNextPC() { return nextPC; }
 247
 248     /** Set the predicted target of this current instruction. */
 249     void setPredTarg(Addr predicted_PC) { predPC = predicted_PC; }
 250
 251     /** Returns the predicted target of the branch. */
 252     Addr readPredTarg() { return predPC; }
 253
 254     /** Returns whether the instruction was predicted taken or not. */
 255     bool predTaken() {
 256         return( predPC != (PC + sizeof(MachInst) ) );
 257     }
 258
 259     /** Returns whether the instruction mispredicted. */
 260     bool mispredicted() { return (predPC != nextPC); }
 261
 262     //
 263     //  Instruction types.  Forward checks to StaticInst object.
 264     //
 265     bool isNop()          const { return staticInst->isNop(); }
 266     bool isMemRef()       const { return staticInst->isMemRef(); }
 267     bool isLoad()         const { return staticInst->isLoad(); }
 268     bool isStore()        const { return staticInst->isStore(); }
 269     bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
 270     bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
 271     bool isCopy()         const { return staticInst->isCopy(); }
 272     bool isInteger()      const { return staticInst->isInteger(); }
 273     bool isFloating()     const { return staticInst->isFloating(); }
 274     bool isControl()      const { return staticInst->isControl(); }
 275     bool isCall()         const { return staticInst->isCall(); }
 276     bool isReturn()       const { return staticInst->isReturn(); }
 277     bool isDirectCtrl()   const { return staticInst->isDirectCtrl(); }
 278     bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
 279     bool isCondCtrl()     const { return staticInst->isCondCtrl(); }
 280     bool isUncondCtrl()   const { return staticInst->isUncondCtrl(); }
 281     bool isThreadSync()   const { return staticInst->isThreadSync(); }
 282     bool isSerializing()  const { return staticInst->isSerializing(); }
 283     bool isMemBarrier()   const { return staticInst->isMemBarrier(); }
 284     bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
 285     bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
 286
 287     /** Returns the opclass of this instruction. */
 288     OpClass opClass() const { return staticInst->opClass(); }
 289
 290     /** Returns the branch target address. */
 291     Addr branchTarget() const { return staticInst->branchTarget(PC); }
 292
 293     /** Number of source registers. */
 294     int8_t numSrcRegs()  const { return staticInst->numSrcRegs(); }
 295
 296     /** Number of destination registers. */
 297     int8_t numDestRegs() const { return staticInst->numDestRegs(); }
 298
 299     // the following are used to track physical register usage
 300     // for machines with separate int & FP reg files
 301     int8_t numFPDestRegs()  const { return staticInst->numFPDestRegs(); }
 302     int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
 303
 304     /** Returns the logical register index of the i'th destination register. */
 305     RegIndex destRegIdx(int i) const
 306     {
 307         return staticInst->destRegIdx(i);
 308     }
 309
 310     /** Returns the logical register index of the i'th source register. */
 311     RegIndex srcRegIdx(int i) const
 312     {
 313         return staticInst->srcRegIdx(i);
 314     }
 315
 316     /** Returns the result of an integer instruction. */
 317     uint64_t readIntResult() { return instResult.integer; }
 318
 319     /** Returns the result of a floating point instruction. */
 320     float readFloatResult() { return instResult.fp; }
 321
 322     /** Returns the result of a floating point (double) instruction. */
 323     double readDoubleResult() { return instResult.dbl; }
 324
 325     //Push to .cc file.
 326     /** Records that one of the source registers is ready. */
 327     void markSrcRegReady()
 328     {
 329         ++readyRegs;
 330         if(readyRegs == numSrcRegs()) {
 331             canIssue = true;
 332         }
 333     }
 334
 335     /** Marks a specific register as ready.
 336      *  @todo: Move this to .cc file.
 337      */
 338     void markSrcRegReady(RegIndex src_idx)
 339     {
 340         ++readyRegs;
 341
 342         _readySrcRegIdx[src_idx] = 1;
 343
 344         if(readyRegs == numSrcRegs()) {
 345             canIssue = true;
 346         }
 347     }
 348
 349     /** Returns if a source register is ready. */
 350     bool isReadySrcRegIdx(int idx) const
 351     {
 352         return this->_readySrcRegIdx[idx];
 353     }
 354
 355     /** Sets this instruction as completed. */
 356     void setCompleted() { completed = true; }
 357
 358     /** Returns whethe or not this instruction is completed. */
 359     bool isCompleted() const { return completed; }
 360
 361     /** Sets this instruction as ready to issue. */
 362     void setCanIssue() { canIssue = true; }
 363
 364     /** Returns whether or not this instruction is ready to issue. */
 365     bool readyToIssue() const { return canIssue; }
 366
 367     /** Sets this instruction as issued from the IQ. */
 368     void setIssued() { issued = true; }
 369
 370     /** Returns whether or not this instruction has issued. */
 371     bool isIssued() const { return issued; }
 372
 373     /** Sets this instruction as executed. */
 374     void setExecuted() { executed = true; }
 375
 376     /** Returns whether or not this instruction has executed. */
 377     bool isExecuted() const { return executed; }
 378
 379     /** Sets this instruction as ready to commit. */
 380     void setCanCommit() { canCommit = true; }
 381
 382     /** Clears this instruction as being ready to commit. */
 383     void clearCanCommit() { canCommit = false; }
 384
 385     /** Returns whether or not this instruction is ready to commit. */
 386     bool readyToCommit() const { return canCommit; }
 387
 388     /** Sets this instruction as squashed. */
 389     void setSquashed() { squashed = true; }
 390
 391     /** Returns whether or not this instruction is squashed. */
 392     bool isSquashed() const { return squashed; }
 393
 394     /** Sets this instruction as squashed in the IQ. */
 395     void setSquashedInIQ() { squashedInIQ = true; }
 396
 397     /** Returns whether or not this instruction is squashed in the IQ. */
 398     bool isSquashedInIQ() const { return squashedInIQ; }
 399
 400     /** Read the PC of this instruction. */
 401     const Addr readPC() const { return PC; }
 402
 403     /** Set the next PC of this instruction (its actual target). */
 404     void setNextPC(uint64_t val) { nextPC = val; }
 405
 406     /** Returns the exec context.
 407      *  @todo: Remove this once the ExecContext is no longer used.
 408      */
 409     ExecContext *xcBase() { return cpuXC->getProxy(); }
 410
 411   private:
 412     /** Instruction effective address.
 413      *  @todo: Consider if this is necessary or not.
 414      */
 415     Addr instEffAddr;
 416     /** Whether or not the effective address calculation is completed.
 417      *  @todo: Consider if this is necessary or not.
 418      */
 419     bool eaCalcDone;
 420
 421   public:
 422     /** Sets the effective address. */
 423     void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; }
 424
 425     /** Returns the effective address. */
 426     const Addr &getEA() const { return instEffAddr; }
 427
 428     /** Returns whether or not the eff. addr. calculation has been completed. */
 429     bool doneEACalc() { return eaCalcDone; }
 430
 431     /** Returns whether or not the eff. addr. source registers are ready. */
 432     bool eaSrcsReady();
 433
 434   public:
 435     /** Load queue index. */
 436     int16_t lqIdx;
 437
 438     /** Store queue index. */
 439     int16_t sqIdx;
 440 };
 441
 442 template<class Impl>
 443 template<class T>
 444 inline Fault
 445 BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
 446 {
 447     MemReqPtr req = new MemReq(addr, cpuXC->getProxy(), sizeof(T), flags);
 448     req->asid = asid;
 449
 450     fault = cpu->translateDataReadReq(req);
 451
 452     // Record key MemReq parameters so we can generate another one
 453     // just like it for the timing access without calling translate()
 454     // again (which might mess up the TLB).
 455     // Do I ever really need this? -KTL 3/05
 456     effAddr = req->vaddr;
 457     physEffAddr = req->paddr;
 458     memReqFlags = req->flags;
 459
 460     /**
 461      * @todo
 462      * Replace the disjoint functional memory with a unified one and remove
 463      * this hack.
 464      */
 465 #if !FULL_SYSTEM
 466     req->paddr = req->vaddr;
 467 #endif
 468
 469     if (fault == NoFault) {
 470         fault = cpu->read(req, data, lqIdx);
 471     } else {
 472         // Return a fixed value to keep simulation deterministic even
 473         // along misspeculated paths.
 474         data = (T)-1;
 475     }
 476
 477     if (traceData) {
 478         traceData->setAddr(addr);
 479         traceData->setData(data);
 480     }
 481
 482     return fault;
 483 }
 484
 485 template<class Impl>
 486 template<class T>
 487 inline Fault
 488 BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
 489 {
 490     if (traceData) {
 491         traceData->setAddr(addr);
 492         traceData->setData(data);
 493     }
 494
 495     MemReqPtr req = new MemReq(addr, cpuXC->getProxy(), sizeof(T), flags);
 496
 497     req->asid = asid;
 498
 499     fault = cpu->translateDataWriteReq(req);
 500
 501     // Record key MemReq parameters so we can generate another one
 502     // just like it for the timing access without calling translate()
 503     // again (which might mess up the TLB).
 504     effAddr = req->vaddr;
 505     physEffAddr = req->paddr;
 506     memReqFlags = req->flags;
 507
 508     /**
 509      * @todo
 510      * Replace the disjoint functional memory with a unified one and remove
 511      * this hack.
 512      */
 513 #if !FULL_SYSTEM
 514     req->paddr = req->vaddr;
 515 #endif
 516
 517     if (fault == NoFault) {
 518         fault = cpu->write(req, data, sqIdx);
 519     }
 520
 521     if (res) {
 522         // always return some result to keep misspeculated paths
 523         // (which will ignore faults) deterministic
 524         *res = (fault == NoFault) ? req->result : 0;
 525     }
 526
 527     return fault;
 528 }
 529
 530 #endif // __CPU_BASE_DYN_INST_HH__