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29 #ifndef __CPU_BASE_DYN_INST_HH__
30 #define __CPU_BASE_DYN_INST_HH__
35 #include "base/fast_alloc.hh"
36 #include "base/trace.hh"
37 #include "config/full_system.hh"
38 #include "cpu/exetrace.hh"
39 #include "cpu/inst_seq.hh"
40 #include "cpu/o3/comm.hh"
41 #include "cpu/static_inst.hh"
42 #include "encumbered/cpu/full/bpred_update.hh"
43 #include "encumbered/cpu/full/op_class.hh"
44 #include "encumbered/cpu/full/spec_memory.hh"
45 #include "encumbered/cpu/full/spec_state.hh"
46 #include "encumbered/mem/functional/main.hh"
50 * Defines a dynamic instruction context.
53 // Forward declaration.
57 class BaseDynInst : public FastAlloc, public RefCounted
60 // Typedef for the CPU.
61 typedef typename Impl::FullCPU FullCPU;
63 /// Binary machine instruction type.
64 typedef TheISA::MachInst MachInst;
65 /// Logical register index type.
66 typedef TheISA::RegIndex RegIndex;
67 /// Integer register index type.
68 typedef TheISA::IntReg IntReg;
71 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
72 MaxInstDestRegs = TheISA::MaxInstDestRegs, //< Max dest regs
75 /** The static inst used by this dyn inst. */
76 StaticInstPtr staticInst;
78 ////////////////////////////////////////////
80 // INSTRUCTION EXECUTION
82 ////////////////////////////////////////////
83 Trace::InstRecord *traceData;
86 Fault read(Addr addr, T &data, unsigned flags);
89 Fault write(T data, Addr addr, unsigned flags,
92 void prefetch(Addr addr, unsigned flags);
93 void writeHint(Addr addr, int size, unsigned flags);
94 Fault copySrcTranslate(Addr src);
95 Fault copy(Addr dest);
97 /** @todo: Consider making this private. */
99 /** Is this instruction valid. */
102 /** The sequence number of the instruction. */
105 /** How many source registers are ready. */
108 /** Is the instruction completed. */
111 /** Can this instruction issue. */
114 /** Has this instruction issued. */
117 /** Has this instruction executed (or made it through execute) yet. */
120 /** Can this instruction commit. */
123 /** Is this instruction squashed. */
126 /** Is this instruction squashed in the instruction queue. */
129 /** Is this a recover instruction. */
132 /** Is this a thread blocking instruction. */
133 bool blockingInst; /* this inst has called thread_block() */
135 /** Is this a thread syncrhonization instruction. */
138 /** The thread this instruction is from. */
141 /** data address space ID, for loads & stores. */
144 /** Pointer to the FullCPU object. */
147 /** Pointer to the exec context. Will not exist in the final version. */
148 CPUExecContext *cpuXC;
150 /** The kind of fault this instruction has generated. */
153 /** The effective virtual address (lds & stores only). */
156 /** The effective physical address. */
159 /** Effective virtual address for a copy source. */
162 /** Effective physical address for a copy source. */
163 Addr copySrcPhysEffAddr;
165 /** The memory request flags (from translation). */
166 unsigned memReqFlags;
168 /** The size of the data to be stored. */
171 /** The data to be stored. */
180 /** The result of the instruction; assumes for now that there's only one
181 * destination register.
185 /** PC of this instruction. */
188 /** Next non-speculative PC. It is not filled in at fetch, but rather
189 * once the target of the branch is truly known (either decode or
194 /** Predicted next PC. */
197 /** Count of total number of dynamic instructions. */
198 static int instcount;
200 /** Whether or not the source register is ready. Not sure this should be
201 * here vs. the derived class.
203 bool _readySrcRegIdx[MaxInstSrcRegs];
206 /** BaseDynInst constructor given a binary instruction. */
207 BaseDynInst(MachInst inst, Addr PC, Addr Pred_PC, InstSeqNum seq_num,
210 /** BaseDynInst constructor given a static inst pointer. */
211 BaseDynInst(StaticInstPtr &_staticInst);
213 /** BaseDynInst destructor. */
217 /** Function to initialize variables in the constructors. */
222 trace_mem(Fault fault, // last fault
223 MemCmd cmd, // last command
224 Addr addr, // virtual address of access
225 void *p, // memory accessed
226 int nbytes); // access size
228 /** Dumps out contents of this BaseDynInst. */
231 /** Dumps out contents of this BaseDynInst into given string. */
232 void dump(std::string &outstring);
234 /** Returns the fault type. */
235 Fault getFault() { return fault; }
237 /** Checks whether or not this instruction has had its branch target
238 * calculated yet. For now it is not utilized and is hacked to be
241 bool doneTargCalc() { return false; }
243 /** Returns the next PC. This could be the speculative next PC if it is
244 * called prior to the actual branch target being calculated.
246 Addr readNextPC() { return nextPC; }
248 /** Set the predicted target of this current instruction. */
249 void setPredTarg(Addr predicted_PC) { predPC = predicted_PC; }
251 /** Returns the predicted target of the branch. */
252 Addr readPredTarg() { return predPC; }
254 /** Returns whether the instruction was predicted taken or not. */
256 return( predPC != (PC + sizeof(MachInst) ) );
259 /** Returns whether the instruction mispredicted. */
260 bool mispredicted() { return (predPC != nextPC); }
263 // Instruction types. Forward checks to StaticInst object.
265 bool isNop() const { return staticInst->isNop(); }
266 bool isMemRef() const { return staticInst->isMemRef(); }
267 bool isLoad() const { return staticInst->isLoad(); }
268 bool isStore() const { return staticInst->isStore(); }
269 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
270 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
271 bool isCopy() const { return staticInst->isCopy(); }
272 bool isInteger() const { return staticInst->isInteger(); }
273 bool isFloating() const { return staticInst->isFloating(); }
274 bool isControl() const { return staticInst->isControl(); }
275 bool isCall() const { return staticInst->isCall(); }
276 bool isReturn() const { return staticInst->isReturn(); }
277 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
278 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
279 bool isCondCtrl() const { return staticInst->isCondCtrl(); }
280 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
281 bool isThreadSync() const { return staticInst->isThreadSync(); }
282 bool isSerializing() const { return staticInst->isSerializing(); }
283 bool isMemBarrier() const { return staticInst->isMemBarrier(); }
284 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
285 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
287 /** Returns the opclass of this instruction. */
288 OpClass opClass() const { return staticInst->opClass(); }
290 /** Returns the branch target address. */
291 Addr branchTarget() const { return staticInst->branchTarget(PC); }
293 /** Number of source registers. */
294 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
296 /** Number of destination registers. */
297 int8_t numDestRegs() const { return staticInst->numDestRegs(); }
299 // the following are used to track physical register usage
300 // for machines with separate int & FP reg files
301 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); }
302 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
304 /** Returns the logical register index of the i'th destination register. */
305 RegIndex destRegIdx(int i) const
307 return staticInst->destRegIdx(i);
310 /** Returns the logical register index of the i'th source register. */
311 RegIndex srcRegIdx(int i) const
313 return staticInst->srcRegIdx(i);
316 /** Returns the result of an integer instruction. */
317 uint64_t readIntResult() { return instResult.integer; }
319 /** Returns the result of a floating point instruction. */
320 float readFloatResult() { return instResult.fp; }
322 /** Returns the result of a floating point (double) instruction. */
323 double readDoubleResult() { return instResult.dbl; }
326 /** Records that one of the source registers is ready. */
327 void markSrcRegReady()
330 if(readyRegs == numSrcRegs()) {
335 /** Marks a specific register as ready.
336 * @todo: Move this to .cc file.
338 void markSrcRegReady(RegIndex src_idx)
342 _readySrcRegIdx[src_idx] = 1;
344 if(readyRegs == numSrcRegs()) {
349 /** Returns if a source register is ready. */
350 bool isReadySrcRegIdx(int idx) const
352 return this->_readySrcRegIdx[idx];
355 /** Sets this instruction as completed. */
356 void setCompleted() { completed = true; }
358 /** Returns whethe or not this instruction is completed. */
359 bool isCompleted() const { return completed; }
361 /** Sets this instruction as ready to issue. */
362 void setCanIssue() { canIssue = true; }
364 /** Returns whether or not this instruction is ready to issue. */
365 bool readyToIssue() const { return canIssue; }
367 /** Sets this instruction as issued from the IQ. */
368 void setIssued() { issued = true; }
370 /** Returns whether or not this instruction has issued. */
371 bool isIssued() const { return issued; }
373 /** Sets this instruction as executed. */
374 void setExecuted() { executed = true; }
376 /** Returns whether or not this instruction has executed. */
377 bool isExecuted() const { return executed; }
379 /** Sets this instruction as ready to commit. */
380 void setCanCommit() { canCommit = true; }
382 /** Clears this instruction as being ready to commit. */
383 void clearCanCommit() { canCommit = false; }
385 /** Returns whether or not this instruction is ready to commit. */
386 bool readyToCommit() const { return canCommit; }
388 /** Sets this instruction as squashed. */
389 void setSquashed() { squashed = true; }
391 /** Returns whether or not this instruction is squashed. */
392 bool isSquashed() const { return squashed; }
394 /** Sets this instruction as squashed in the IQ. */
395 void setSquashedInIQ() { squashedInIQ = true; }
397 /** Returns whether or not this instruction is squashed in the IQ. */
398 bool isSquashedInIQ() const { return squashedInIQ; }
400 /** Read the PC of this instruction. */
401 const Addr readPC() const { return PC; }
403 /** Set the next PC of this instruction (its actual target). */
404 void setNextPC(uint64_t val) { nextPC = val; }
406 /** Returns the exec context.
407 * @todo: Remove this once the ExecContext is no longer used.
409 ExecContext *xcBase() { return cpuXC->getProxy(); }
412 /** Instruction effective address.
413 * @todo: Consider if this is necessary or not.
416 /** Whether or not the effective address calculation is completed.
417 * @todo: Consider if this is necessary or not.
422 /** Sets the effective address. */
423 void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; }
425 /** Returns the effective address. */
426 const Addr &getEA() const { return instEffAddr; }
428 /** Returns whether or not the eff. addr. calculation has been completed. */
429 bool doneEACalc() { return eaCalcDone; }
431 /** Returns whether or not the eff. addr. source registers are ready. */
435 /** Load queue index. */
438 /** Store queue index. */
445 BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
447 MemReqPtr req = new MemReq(addr, cpuXC->getProxy(), sizeof(T), flags);
450 fault = cpu->translateDataReadReq(req);
452 // Record key MemReq parameters so we can generate another one
453 // just like it for the timing access without calling translate()
454 // again (which might mess up the TLB).
455 // Do I ever really need this? -KTL 3/05
456 effAddr = req->vaddr;
457 physEffAddr = req->paddr;
458 memReqFlags = req->flags;
462 * Replace the disjoint functional memory with a unified one and remove
466 req->paddr = req->vaddr;
469 if (fault == NoFault) {
470 fault = cpu->read(req, data, lqIdx);
472 // Return a fixed value to keep simulation deterministic even
473 // along misspeculated paths.
478 traceData->setAddr(addr);
479 traceData->setData(data);
488 BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
491 traceData->setAddr(addr);
492 traceData->setData(data);
495 MemReqPtr req = new MemReq(addr, cpuXC->getProxy(), sizeof(T), flags);
499 fault = cpu->translateDataWriteReq(req);
501 // Record key MemReq parameters so we can generate another one
502 // just like it for the timing access without calling translate()
503 // again (which might mess up the TLB).
504 effAddr = req->vaddr;
505 physEffAddr = req->paddr;
506 memReqFlags = req->flags;
510 * Replace the disjoint functional memory with a unified one and remove
514 req->paddr = req->vaddr;
517 if (fault == NoFault) {
518 fault = cpu->write(req, data, sqIdx);
522 // always return some result to keep misspeculated paths
523 // (which will ignore faults) deterministic
524 *res = (fault == NoFault) ? req->result : 0;
530 #endif // __CPU_BASE_DYN_INST_HH__