Check in of new CPU. This checkin works under non-Fullsystem mode, with no caches.
[gem5.git] / cpu / beta_cpu / alpha_params.hh
1 #ifndef __ALPHA_SIMPLE_PARAMS_HH__
2 #define __ALPHA_SIMPLE_PARAMS_HH__
3
4 //Forward declarations
5 class System;
6 class AlphaITB;
7 class AlphaDTB;
8 class FunctionalMemory;
9 class Process;
10 class MemInterface;
11
12 /**
13 * This file defines the parameters that will be used for the AlphaFullCPU.
14 * This must be defined externally so that the Impl can have a params class
15 * defined that it can pass to all of the individual stages.
16 */
17
18 class AlphaSimpleParams
19 {
20 public:
21 std::string name;
22 int numberOfThreads;
23
24 #ifdef FULL_SYSTEM
25 System *_system;
26 AlphaITB *itb; AlphaDTB *dtb;
27 Tick freq;
28 #else
29 std::vector<Process *> workload;
30 Process *process;
31 short asid;
32 #endif // FULL_SYSTEM
33
34 FunctionalMemory *mem;
35
36 Counter maxInstsAnyThread;
37 Counter maxInstsAllThreads;
38 Counter maxLoadsAnyThread;
39 Counter maxLoadsAllThreads;
40
41 //
42 // Caches
43 //
44 MemInterface *icacheInterface;
45 MemInterface *dcacheInterface;
46
47 unsigned decodeToFetchDelay;
48 unsigned renameToFetchDelay;
49 unsigned iewToFetchDelay;
50 unsigned commitToFetchDelay;
51 unsigned fetchWidth;
52
53 unsigned renameToDecodeDelay;
54 unsigned iewToDecodeDelay;
55 unsigned commitToDecodeDelay;
56 unsigned fetchToDecodeDelay;
57 unsigned decodeWidth;
58
59 unsigned iewToRenameDelay;
60 unsigned commitToRenameDelay;
61 unsigned decodeToRenameDelay;
62 unsigned renameWidth;
63
64 unsigned commitToIEWDelay;
65 unsigned renameToIEWDelay;
66 unsigned issueToExecuteDelay;
67 unsigned issueWidth;
68 unsigned executeWidth;
69 unsigned executeIntWidth;
70 unsigned executeFloatWidth;
71
72 unsigned iewToCommitDelay;
73 unsigned renameToROBDelay;
74 unsigned commitWidth;
75 unsigned squashWidth;
76
77 unsigned numPhysIntRegs;
78 unsigned numPhysFloatRegs;
79 unsigned numIQEntries;
80 unsigned numROBEntries;
81
82 bool defReg;
83 };
84
85 #endif