cpu/beta_cpu/decode.hh

   1 // Todo:
   2 // Add a couple of the branch fields to DynInst.  Figure out where DynInst
   3 // should try to compute the target of a PC-relative branch.  Try to avoid
   4 // having so many returns within the code.
   5 // Fix up squashing too, as it's too
   6 // dependent upon the iew stage continually telling it to squash.
   7
   8 #ifndef __CPU_BETA_CPU_SIMPLE_DECODE_HH__
   9 #define __CPU_BETA_CPU_SIMPLE_DECODE_HH__
  10
  11 #include <queue>
  12
  13 #include "base/statistics.hh"
  14 #include "base/timebuf.hh"
  15
  16 template<class Impl>
  17 class SimpleDecode
  18 {
  19   private:
  20     // Typedefs from the Impl.
  21     typedef typename Impl::ISA ISA;
  22     typedef typename Impl::FullCPU FullCPU;
  23     typedef typename Impl::DynInstPtr DynInstPtr;
  24     typedef typename Impl::Params Params;
  25     typedef typename Impl::CPUPol CPUPol;
  26
  27     // Typedefs from the CPU policy.
  28     typedef typename CPUPol::FetchStruct FetchStruct;
  29     typedef typename CPUPol::DecodeStruct DecodeStruct;
  30     typedef typename CPUPol::TimeStruct TimeStruct;
  31
  32     // Typedefs from the ISA.
  33     typedef typename ISA::Addr Addr;
  34
  35   public:
  36     // The only time decode will become blocked is if dispatch becomes
  37     // blocked, which means IQ or ROB is probably full.
  38     enum Status {
  39         Running,
  40         Idle,
  41         Squashing,
  42         Blocked,
  43         Unblocking
  44     };
  45
  46   private:
  47     // May eventually need statuses on a per thread basis.
  48     Status _status;
  49
  50   public:
  51     SimpleDecode(Params &params);
  52
  53     void regStats();
  54
  55     void setCPU(FullCPU *cpu_ptr);
  56
  57     void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
  58
  59     void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr);
  60
  61     void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
  62
  63     void tick();
  64
  65     void decode();
  66
  67     // Might want to make squash a friend function.
  68     void squash();
  69
  70   private:
  71     void block();
  72
  73     inline void unblock();
  74
  75     void squash(DynInstPtr &inst);
  76
  77     // Interfaces to objects outside of decode.
  78     /** CPU interface. */
  79     FullCPU *cpu;
  80
  81     /** Time buffer interface. */
  82     TimeBuffer<TimeStruct> *timeBuffer;
  83
  84     /** Wire to get rename's output from backwards time buffer. */
  85     typename TimeBuffer<TimeStruct>::wire fromRename;
  86
  87     /** Wire to get iew's information from backwards time buffer. */
  88     typename TimeBuffer<TimeStruct>::wire fromIEW;
  89
  90     /** Wire to get commit's information from backwards time buffer. */
  91     typename TimeBuffer<TimeStruct>::wire fromCommit;
  92
  93     /** Wire to write information heading to previous stages. */
  94     // Might not be the best name as not only fetch will read it.
  95     typename TimeBuffer<TimeStruct>::wire toFetch;
  96
  97     /** Decode instruction queue. */
  98     TimeBuffer<DecodeStruct> *decodeQueue;
  99
 100     /** Wire used to write any information heading to rename. */
 101     typename TimeBuffer<DecodeStruct>::wire toRename;
 102
 103     /** Fetch instruction queue interface. */
 104     TimeBuffer<FetchStruct> *fetchQueue;
 105
 106     /** Wire to get fetch's output from fetch queue. */
 107     typename TimeBuffer<FetchStruct>::wire fromFetch;
 108
 109     /** Skid buffer between fetch and decode. */
 110     std::queue<FetchStruct> skidBuffer;
 111
 112   private:
 113     //Consider making these unsigned to avoid any confusion.
 114     /** Rename to decode delay, in ticks. */
 115     unsigned renameToDecodeDelay;
 116
 117     /** IEW to decode delay, in ticks. */
 118     unsigned iewToDecodeDelay;
 119
 120     /** Commit to decode delay, in ticks. */
 121     unsigned commitToDecodeDelay;
 122
 123     /** Fetch to decode delay, in ticks. */
 124     unsigned fetchToDecodeDelay;
 125
 126     /** The width of decode, in instructions. */
 127     unsigned decodeWidth;
 128
 129     /** The instruction that decode is currently on.  It needs to have
 130      *  persistent state so that when a stall occurs in the middle of a
 131      *  group of instructions, it can restart at the proper instruction.
 132      */
 133     unsigned numInst;
 134
 135     Stats::Scalar<> decodeIdleCycles;
 136     Stats::Scalar<> decodeBlockedCycles;
 137     Stats::Scalar<> decodeUnblockCycles;
 138     Stats::Scalar<> decodeSquashCycles;
 139     Stats::Scalar<> decodeBranchMispred;
 140     Stats::Scalar<> decodeControlMispred;
 141     Stats::Scalar<> decodeDecodedInsts;
 142     Stats::Scalar<> decodeSquashedInsts;
 143 };
 144
 145 #endif // __CPU_BETA_CPU_SIMPLE_DECODE_HH__