2 // Fix up trap and barrier handling.
3 // May want to have different statuses to differentiate the different stall
6 #ifndef __SIMPLE_RENAME_HH__
7 #define __SIMPLE_RENAME_HH__
11 #include "base/timebuf.hh"
13 // Will need rename maps for both the int reg file and fp reg file.
14 // Or change rename map class to handle both. (RegFile handles both.)
19 // Typedefs from the Impl.
20 typedef typename Impl::ISA ISA;
21 typedef typename Impl::CPUPol CPUPol;
22 typedef typename Impl::DynInstPtr DynInstPtr;
23 typedef typename Impl::FullCPU FullCPU;
24 typedef typename Impl::Params Params;
26 typedef typename CPUPol::FetchStruct FetchStruct;
27 typedef typename CPUPol::DecodeStruct DecodeStruct;
28 typedef typename CPUPol::RenameStruct RenameStruct;
29 typedef typename CPUPol::TimeStruct TimeStruct;
31 // Typedefs from the CPUPol
32 typedef typename CPUPol::FreeList FreeList;
33 typedef typename CPUPol::RenameMap RenameMap;
35 // Typedefs from the ISA.
36 typedef typename ISA::Addr Addr;
39 // Rename will block if ROB becomes full or issue queue becomes full,
40 // or there are no free registers to rename to.
41 // Only case where rename squashes is if IEW squashes.
55 SimpleRename(Params ¶ms);
59 void setCPU(FullCPU *cpu_ptr);
61 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
63 void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
65 void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr);
67 void setRenameMap(RenameMap *rm_ptr);
69 void setFreeList(FreeList *fl_ptr);
82 inline void unblock();
86 void removeFromHistory(InstSeqNum inst_seq_num);
88 inline void renameSrcRegs(DynInstPtr &inst);
90 inline void renameDestRegs(DynInstPtr &inst);
92 inline int calcFreeROBEntries();
94 inline int calcFreeIQEntries();
96 /** Holds the previous information for each rename.
97 * Note that often times the inst may have been deleted, so only access
98 * the pointer for the address and do not dereference it.
100 struct RenameHistory {
101 RenameHistory(InstSeqNum _instSeqNum, RegIndex _archReg,
102 PhysRegIndex _newPhysReg, PhysRegIndex _prevPhysReg)
103 : instSeqNum(_instSeqNum), archReg(_archReg),
104 newPhysReg(_newPhysReg), prevPhysReg(_prevPhysReg),
109 /** Constructor used specifically for cases where a place holder
110 * rename history entry is being made.
112 RenameHistory(InstSeqNum _instSeqNum)
113 : instSeqNum(_instSeqNum), archReg(0), newPhysReg(0),
114 prevPhysReg(0), placeHolder(true)
118 InstSeqNum instSeqNum;
120 PhysRegIndex newPhysReg;
121 PhysRegIndex prevPhysReg;
125 std::list<RenameHistory> historyBuffer;
127 /** CPU interface. */
130 // Interfaces to objects outside of rename.
131 /** Time buffer interface. */
132 TimeBuffer<TimeStruct> *timeBuffer;
134 /** Wire to get IEW's output from backwards time buffer. */
135 typename TimeBuffer<TimeStruct>::wire fromIEW;
137 /** Wire to get commit's output from backwards time buffer. */
138 typename TimeBuffer<TimeStruct>::wire fromCommit;
140 /** Wire to write infromation heading to previous stages. */
141 // Might not be the best name as not only decode will read it.
142 typename TimeBuffer<TimeStruct>::wire toDecode;
144 /** Rename instruction queue. */
145 TimeBuffer<RenameStruct> *renameQueue;
147 /** Wire to write any information heading to IEW. */
148 typename TimeBuffer<RenameStruct>::wire toIEW;
150 /** Decode instruction queue interface. */
151 TimeBuffer<DecodeStruct> *decodeQueue;
153 /** Wire to get decode's output from decode queue. */
154 typename TimeBuffer<DecodeStruct>::wire fromDecode;
156 /** Skid buffer between rename and decode. */
157 std::queue<DecodeStruct> skidBuffer;
159 /** Rename map interface. */
160 SimpleRenameMap *renameMap;
162 /** Free list interface. */
165 /** Delay between iew and rename, in ticks. */
166 int iewToRenameDelay;
168 /** Delay between decode and rename, in ticks. */
169 int decodeToRenameDelay;
171 /** Delay between commit and rename, in ticks. */
172 unsigned commitToRenameDelay;
174 /** Rename width, in instructions. */
175 unsigned renameWidth;
177 /** Commit width, in instructions. Used so rename knows how many
178 * instructions might have freed registers in the previous cycle.
180 unsigned commitWidth;
182 /** The instruction that rename is currently on. It needs to have
183 * persistent state so that when a stall occurs in the middle of a
184 * group of instructions, it can restart at the proper instruction.
188 Stats::Scalar<> renameSquashCycles;
189 Stats::Scalar<> renameIdleCycles;
190 Stats::Scalar<> renameBlockCycles;
191 Stats::Scalar<> renameUnblockCycles;
192 Stats::Scalar<> renameRenamedInsts;
193 Stats::Scalar<> renameSquashedInsts;
194 Stats::Scalar<> renameROBFullEvents;
195 Stats::Scalar<> renameIQFullEvents;
196 Stats::Scalar<> renameFullRegistersEvents;
197 Stats::Scalar<> renameRenamedOperands;
198 Stats::Scalar<> renameRenameLookups;
199 Stats::Scalar<> renameHBPlaceHolders;
200 Stats::Scalar<> renameCommittedMaps;
201 Stats::Scalar<> renameUndoneMaps;
202 Stats::Scalar<> renameValidUndoneMaps;
205 #endif // __SIMPLE_RENAME_HH__